HY57V641620ET-H Hynix Semiconductor, HY57V641620ET-H Datasheet

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HY57V641620ET-H

Manufacturer Part Number
HY57V641620ET-H
Description
HY57V641620ET-H64Mb Synchronous DRAM based on 1M x 4Bank x16 I/O
Manufacturer
Hynix Semiconductor
Datasheet

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Document Title
4Bank x 1M x 16bits Synchronous DRAM
Revision History
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 1.5 / Feb. 2005
64Mb Synchronous DRAM based on 1M x 4Bank x16 I/O
Revision No.
1.0
1.1
1.2
1.3
1.4
1.5
First Version Release
1. Changed tOH: 2.0 --> 2.5
1. Changed Input High/Low Voltage (Page 08)
2. Changed DC characteristics (Page 09)
3. Changed Clock High / Low pulse width Time (Page 11)
4. Changed tAC Time (Page11)
5. Changed tRRD Time (Page12)
1. Corrected Revision No.: 2.0 -> 1.1
2. Deleted Remark at Revision History
3. Corrected AC OPERATING CONDITION
4. Changed DC OPERATING CONDITION
1. Modified note for Super Low Power in ORDERING INFORMATION
1. Corrected PIN ASSIGNMENT A12 to NC
1. Corrected comments for overshoot and undershoot
- IDD2NS: 18mA -> 15mA
- IDD5:210 / 195 / 180mA -> 170 / 160 / 150mA
- CL 50pF -> 30pF
- VIH MAX VDDQ+2.0 -> VDDQ+0.3 and Typ 3.3 -> 3.0
- VIL MIN VSSQ-2.0 -> -0.3
[tCK = 7 & 7.5 (CL3) Product]
[Speed 200 / 166 / 143 / 133MHz]
History
Draft Date
Nov. 2004
Dec. 2004
Dec. 2004
Feb. 2005
Jan. 2005
Jan. 2005
Remark
1

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HY57V641620ET-H Summary of contents

Page 1

Synchronous DRAM based 4Bank x16 I/O Document Title 4Bank 16bits Synchronous DRAM Revision History Revision No. First Version Release 1.0 1. Changed tOH: 2.0 --> 2.5 [tCK = 7 & 7.5 (CL3) Product] ...

Page 2

... HY57V641620E(L/S)T(P)-H Note: 1. HY57V641620ET Series: Normal power, Leaded. 2. HY57V641620ELT Series: Low power, Leaded. 3. HY57V641620EST Series: Super Low power, Leaded. 4. HY57V641620ETP Series: Normal power, Lead Free. 5. HY57V641620ELTP Series: Low power, Lead Free. 6. HY57V641620ESTP Series: Super Low Power, Lead Free Rev. 1.5 / Feb. 2005 Synchronous DRAM Memory 64Mbit (4Mx16bit) • ...

Page 3

PIN ASSIGNMENTS VDD 1 DQ0 2 VDDQ 3 DQ1 4 DQ2 5 VSSQ 6 DQ3 7 DQ4 8 VDDQ 9 DQ5 10 DQ6 11 VSSQ 12 DQ7 13 VDD 14 LDQM 15 /WE 16 /CAS 17 /RAS 18 /CS 19 ...

Page 4

PIN DESCRIPTION SYMBOL TYPE CLK Clock CKE Clock Enable CS Chip Select BA0, BA1 Bank Address A0 ~ A11 Address Row Address Strobe, RAS, CAS, WE Column Address Strobe, Write Enable UDQM, LDQM Data Input/Output Mask DQ0 ~ DQ15 Data ...

Page 5

FUNCTIONAL BLOCK DIAGRAM 1Mbit x 4banks x 16 I/O Synchronous DRAM Self refresh logic & timer CLK Row Active CKE CS RAS Refresh CAS Column Active WE U/LDQM Bank Select Address A0 Register A1 A11 BA1 BA0 Rev. 1.5 / ...

Page 6

BASIC FUNCTIONAL DESCRIPTION Mode Register BA1 BA0 A11 A10 Code A9 Write Mode 0 Burst Read and Burst Write 1 Burst Read and Single Write CAS Latency CAS Latency ...

Page 7

ABSOLUTE MAXIMUM RATING Parameter Ambient Temperature Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Short Circuit Output Current Power Dissipation Soldering Temperature / Time DC OPERATING CONDITION Parameter Power Supply Voltage Input High ...

Page 8

CAPACITANCE ( Parameter Input capacitance Data input / output capacitance DC CHARACTERRISTICS I Parameter Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Note 3.3V, All other ...

Page 9

... Specified values are measured with the output open DD1 DD4 2. Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II 3. HY57V641620ET(P) Series: Normal Power HY57V641620ELT(P) Series: Low Power HY57V641620EST(P) Series: Super Low Power Rev. 1.5 / Feb. 2005 ...

Page 10

AC CHARACTERISTICS I Parameter System Clock Cycle Time Clock High Pulse Width Clock Low Pulse Width Access Time From Clock Data-out Hold Time Data-Input Setup Time Data-Input Hold ...

Page 11

AC CHARACTERISTICS II Parameter RAS Cycle Time Operation RAS Cycle Time Auto Refresh tRRC RAS to CAS Delay RAS Active Time RAS Precharge Time RAS to RAS Bank Active Delay CAS to CAS Delay Write Command to Data-In De- lay ...

Page 12

COMMAND TRUTH TABLE Command CKEn-1 Mode Register Set H No Operation H Bank Active H Read H Read with Autopre- charge Write H Write with Autopre- charge Precharge All Banks H Precharge selected Bank Burst Stop H DQM H Auto ...

Page 13

PACKAGE INFORMATION 400mil 54pin Thin Small Outline Package 22.327(0.8790) 22.149(0.8720) 0.150(0.0059) 0.050(0.0020) 0.400(0.016) 0.80(0.0315)BSC 0.300(0.012) Rev. 1.5 / Feb. 2005 Synchronous DRAM Memory 64Mbit (4Mx16bit) HY57V641620E(L/S)T(P) Series UNIT : mm(inch) 11.938(0.4700) 11.735(0.4620) 10.262(0.4040) 10.058(0.3960) 5deg 0.597(0.0235) 0deg 0.406(0.0160) 1.194(0.0470) 0.991(0.0390) ...

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