HY5DU281622ET-5 Hynix Semiconductor, HY5DU281622ET-5 Datasheet
HY5DU281622ET-5
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HY5DU281622ET-5 Summary of contents
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... GDDR SDRAM This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any respon- sibility for use of circuits described. No patent licenses are implied. Rev. 0.5 / Jan. 2005 HY5DU281622ET HY5DU281622ET 1 ...
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... Insert tDSS/tDSH Parameter 0.3 tPDEX value Change 0.4 tRC_APCG changed to 12 clock from 11 clock at 166Mhz speed bin 0.5 166Mhz speed bin delete, AC parameter change (tRC_APCG at 200Mhz) Rev. 0.5 / Jan. 2005 History HY5DU281622ET Draft Date Remark July 2003 Oct. 2003 Mar. 2004 Oct. 2004 Jan. 2005 2 ...
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... HY5DU281622ET-26 HY5DU281622ET-28 VDD/VDDQ=2.8V HY5DU281622ET-30 HY5DU281622ET-33 HY5DU281622ET-36 HY5DU281622ET-4 VDD/VDDQ=2.5V HY5DU281622ET-5 Rev. 0.5 / Jan. 2005 power supply rising and falling edges of the data strobe • All addresses and control inputs except Data, Data power supply strobes and Data masks latched on the rising edges of the clock • ...
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... X 875mil 16 66pin TSOP - 0.65mm pin pitch ROW AND COLUMN ADDRESS TABLE ITEMS Organization Row Address Refresh HY5DU281622ET VSS 66 DQ15 65 64 VSSQ 63 DQ14 62 DQ13 61 VDDQ 60 DQ12 59 DQ11 58 VSSQ 57 DQ10 56 DQ9 55 VDDQ DQ8 54 NC ...
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... Used to capture write data. LDQS corresponds to the data on DQ0-Q7; UDQS corresponds to the data on DQ8-Q15 Data input / output pin : Data Bus Power supply for internal circuits and input buffers. Power supply for output buffers for noise immunity. Reference voltage for inputs for SSTL interface. No connection. HY5DU281622ET 5 ...
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... Rev. 0.5 / Jan. 2005 Write Data Register 2-bit Prefetch Unit 32 Bank 2Mx16/Bank0 Control 2Mx16/Bank1 2Mx16/Bank2 2Mx16/Bank3 Row Decoder Column Decoder Column Address Counter CLK /CLK Register HY5DU281622ET LDQS, UDQS Data Strobe CLK_DLL Transmitter Data Strobe LDQS Receiver UDQS DLL Block Mode DS DQ[0:15] 6 ...
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... HY5DU281622ET A10/ CAS WE ADDR code code ...
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... LDM corresponds to the data on DQ0-Q7 and UDM corresponds to the data on DQ8-Q15 3. In here, Don’t Care means logical value only, it doesn’t mean ’Don’t care for DC level of each signals’. DC level should be out IHmin ILmax Rev. 0.5 / Jan. 2005 /CS, /RAS, CKEn /CAS, / HY5DU281622ET A8 ADDR Note 1,2,3 1,2,3 8 ...
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... OPCODE BA, CA, AP READ/READAP L L BA, CA, AP WRITE/WRITEAP HY5DU281622ET Command Action DSEL NOP or power down NOP NOP or power down BST ILLEGAL ILLEGAL ILLEGAL ACT Row Activation PRE/PALL NOP AREF/SREF Auto Refresh or Self Refresh MRS Mode Register Set ...
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... BA, CA, AP READ/READAP L L BA, CA, AP WRITE/WRITEAP OPCODE HY5DU281622ET Command Action ACT ILLEGAL PRE/PALL Term burst, precharge AREF/SREF ILLEGAL MRS ILLEGAL DSEL Continue burst to end NOP Continue burst to end BST ILLEGAL ILLEGAL ILLEGAL ACT ILLEGAL ...
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... OPCODE BA, CA, AP READ/READAP HY5DU281622ET Command Action DSEL NOP - Enter ROW ACT after tRCD NOP NOP - Enter ROW ACT after tRCD BST ILLEGAL ILLEGAL ILLEGAL ACT ILLEGAL PRE/PALL ILLEGAL AREF/SREF ILLEGAL MRS ILLEGAL DSEL ...
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... H BA, CA, AP READ/READAP L L BA, CA, AP WRITE/WRITEAP OPCODE HY5DU281622ET Command Action ILLEGAL ACT ILLEGAL PRE/PALL ILLEGAL AREF/SREF ILLEGAL MRS ILLEGAL DSEL NOP - Enter IDLE after tMRD NOP NOP - Enter IDLE after tMRD BST ILLEGAL ILLEGAL ILLEGAL ...
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... HY5DU281622ET /ADD Action X INVALID X Exit self refresh, enter idle after tSREX X Exit self refresh, enter idle after tSREX X ILLEGAL X ILLEGAL X ILLEGAL X NOP, continue self refresh X INVALID X Exit power down, enter idle ...
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... IDLE SREX PDEN PDEX AREF ACT POWER DOWN PDEN PDEX BANK ACTIVE WRITE READ WITH WITH AUTOPRE- AUTOPRE- CHARGE CHARGE WRITE PRE- CHARGE POWER-UP POWER APPLIED HY5DU281622ET SELF REFRESH AUTO REFRESH BST READ READAP READ WRITEAP PRE(PALL) Command Input Automatic Sequence 14 ...
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... DLL) 7. Issue Precharge commands for all banks of the device. 8. Issue 2 or more Auto Refresh commands. Rev. 0.5 / Jan. 2005 Sequencing Voltage relationship to avoid latch-up After or with VDD After or with VDDQ After or with VDDQ HY5DU281622ET < VDD + 0.3V < VDDQ + 0.3V < VDDQ + 0.3V 15 ...
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... CODE CODE CODE tRP tMRD tMRD EMRS Set MRS Set Precharge All Precharge All Reset DLL (with A8=H) * 200 cycle(tXSRD are required (for DLL locking) before Read Command HY5DU281622ET AREF MRS ACT CODE CODE CODE CODE CODE CODE tRP tRFC tMRD ...
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... Yes CAS Latency Reserved Reserved Reserved Reserved Reserved HY5DU281622ET Burst Length Burst Length Sequential Reserved Reserved Reserved ...
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... HY5DU281622ET Interleave ...
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... This device supports both Half strength driver and Matched impedance driver, intended for lighter load and/or point-to- point environments. Half strength driver is to define about 50% of Full drive strength which is specified to be SSTL_2, Class II, and Matched impedance driver, about 30% of Full drive strength. Rev. 0.5 / Jan. 2005 HY5DU281622ET 19 ...
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... All bits in RFU address fields must be programmed to Zero, all other states are reserved for future usage. Rev. 0.5 / Jan. 2005 RFU HY5DU281622ET DLL A0 DLL enable 0 Enable 1 Diable Output Driver Impedance Control Full Half (60%) Reserved Weak (33%) 20 ...
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... DDQ 0.15 IH REF V -0 0.04 TT REF V 0.49*V 0.5*V REF DDQ . DD o (TA Voltage referenced to V Min 0. =0V. IN HY5DU281622ET Rating -55 ~ 125 -0.5 ~ 3.6 -0.5 ~ 3.6 -0 260 ⋅ 0V) SS Typ Max Unit 2.5 2.625 V 2.5 2.625 V 2.8 2.9 V 2.8 2 0.3 V DDQ - V - 0.15 V REF 0.04 V REF REF 0 ...
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... I =0mA All banks active ≥ (min), RC RFC All banks active CKE ≤ 0.2V Four bank interleaving with BL=4, Refer to the following page for detailed test condition HY5DU281622ET = 0V) SS Speed 230 220 210 200 190 230 220 210 ...
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... I =0mA All banks active ≥ (min), RC RFC All banks active CKE ≤ 0.2V Four bank interleaving with BL=4, Refer to the following page for detailed test condition HY5DU281622ET = 0V) SS Speed Unit 180 170 160 mA 180 170 160 ...
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... C, Voltage referenced to V Symbol Min 0.45 IH(AC) REF V IL(AC) V 0.7 ID(AC) V 0.5*V -0.2 IX(AC) DDQ of the transmitting device and must track variations in the DC level of the same. DDQ o (TA Voltage referenced to VSS = 0V HY5DU281622ET = 0V) SS Max Unit Note 0.45 V REF V + 0.6 V DDQ 0.5*V +0.2 V DDQ Value Unit V x 0.5 V DDQ ...
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... The area between the overshoot signal and GND must be less than or equal to(See below Fig Volts ( Max. area=2.4V-ns -3 Rev. 0.5 / Jan. 2005 Parameter Time(ns) Parameter Time(ns) HY5DU281622ET 200MHz Specifications 1.5 V 1.5 V 4.5 V-nS 4.5 V-nS Max. amplitude=1. Ground 5 6 200MHz Specifications 1.2 V 1.2 V 2.4 V-nS 2.4 V-nS Max. amplitude=1. Ground ...
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... CL 0.45 0. 0.45 0. -0.55 0.55 t DQSCK -0.55 0.55 t DQSQ - 0.35 tHPmin -tQHS tCH min t - 0.35 QHS DQSH 0.4 0.6 t DQSL 0.4 0.6 t 0.85 1.15 DQSS 0.35 - HY5DU281622ET 26 28 Min Max Min Max 100K 14 100K 2 2.8 6 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 -0.6 ...
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... Signal transitions through the DC region must be monotonic. Rev. 0.5 / Jan. 2005 25 Symbol Min Max Min tDSS 3.0 - 3.0 tDSH 3.0 - 3.0 t WPRES WPREH 0.35 - 0.35 t WPST 0.4 0.6 0.4 t MRD 200 - 200 XSC 2tCK 2tCK t - PDEX + tIS + tIS t REFI - 7.8 - HY5DU281622ET 26 28 Unit Note Max Min Max 0.6 0.4 0 200 - 2tCK tIS us 7 ...
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... 0.45 0.55 t 0.45 0. -0.6 0 DQSCK -0.6 0.6 t DQSQ - 0.35 tHPmin -tQHS tCH min t QHS - 0. DQSH 0.4 0.6 t DQSL 0.4 0.6 t DQSS 0.85 1. 0.35 - HY5DU281622ET 33 36 Min Max Min Max 100K 11 100K 3.3 6 3.6 10 0.45 0.55 0.45 0.55 0.45 0.55 ...
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... Rev. 0.5 / Jan. 2005 30 Symbol Min Max Min tDSS 0.3 - 0.3 tDSH 0.3 - 0.3 t RPRE 0.9 1.1 0.9 t RPST 0.4 0.6 0.4 t WPRES 0.35 - 0.35 WPREH t WPST 0.4 0.6 0.4 t MRD XSC 200 - 200 2tCK 2tCK t PDEX - + tIS + tIS t REFI - 7.8 - HY5DU281622ET 33 36 Unit Note Max Min Max 1.1 0.9 1.1 CK 0.6 0 0.6 0.4 0 200 - 2tCK tIS us 7 ...
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... RRD t CCD DRL t DAL -0.6 t DQSCK -0.6 t DQSQ - tHPmin t QH -tQHS tCH min t - QHS 0.75 t DQSH 0.4 t DQSL 0.4 t 0.85 DQSS HY5DU281622ET 4 5 Unit Max Min Max - 100K 8 100K - 0.55 0.45 0.55 0.55 0.45 0.55 0.6 -0.65 0.65 0.6 -0.55 0.55 0.4 - ...
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... Signal transitions through the DC region must be monotonic. Rev. 0.5 / Jan. 2005 4 Symbol Min Max tDSS 0.3 - tDSH 0 RPRE 0.9 1.1 t 0.4 0.6 RPST t WPRES WPREH 0. WPST 0.4 0 MRD t 200 - XSC 2tCK t - PDEX + tIS t - 7.8 REFI HY5DU281622ET 5 Unit Note Min Max 0.9 1.1 CK 0 0.4 0 200 - 4 2tCK tIS us - 7.8 31 ...
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... Rev. 0.5 / Jan. 2005 tRC_APCG tRFC tRAS tRCDRD HY5DU281622ET tRCDWR tRP tDAL Unit ...
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... These values are guaranteed by design and are tested on a sample basis only. OUTPUT LOAD CIRCUIT Output Rev. 0.5 / Jan. 2005 Pin CK, /CK All other input-only pins DQ, DQS /2, V peak-to-peak = 0.2V O DDQ =50Ω T Zo=50Ω V REF C =30pF L HY5DU281622ET Symbol Min Max Unit ...
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... PACKAGE INFORMATION 400mil 66pin Thin Small Outline Package 0.65 (0.0256) BSC 1.194 (0.0470) 0.991 (0.0390) Rev. 0.5 / Jan. 2005 BASE PLANE 22.33 (0.879) 22.12 (0.871) 0.35 (0.0138) 0.25 (0.0098) SEATING PLANE HY5DU281622ET Unit : mm(Inch) 11.94 (0.470) 11.79 (0.462) 10.26 (0.404) 10.05 (0.396 Deg. 0.15 (0.0059) 0.597 (0.0235) 0.210 (0.0083) 0.05 (0.0020) 0.406 (0.0160) ...