LH28F640BFHG-PBTLZ7 Sharp, LH28F640BFHG-PBTLZ7 Datasheet
LH28F640BFHG-PBTLZ7
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LH28F640BFHG-PBTLZ7 Summary of contents
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... Flash Memory LH28F640BFHG-PBTLZ7 Date Apr. 3. 2003 ...
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Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. When using the products covered herein, please observe ...
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CSP (8mm 11mm) Pinout ..... 3 Pin Descriptions.......................................................... 4 Simultaneous Operation Modes Allowed with Four Planes .................................. 5 Memory Map .............................................................. 6 Identifier Codes and OTP Address for Read Operation ............................................. 7 Identifier Codes and OTP Address ...
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... Fast program capability is provided through the use of high speed Page Buffer Program. Special OTP (One Time Program) block provides an area to store permanent code such as a unique number. * ETOX is a trademark of Intel Corporation. LHF64FD5 LH28F640BFHG-PBTLZ7 64Mbit (4Mbit 16) Flexible Blocking Architecture • Eight 4K-word Parameter Blocks • ...
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WE# RST CCQ 15 ...
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Symbol Type A -A ADDRESS INPUTS: Inputs for addresses. 64M: A INPUT 0 21 DATA INPUTS/OUTPUTS: Inputs data and commands during CUI (Command User Interface) write cycles, outputs data during memory array, status register, query code, INPUT/ DQ -DQ identifier ...
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Table 2. Simultaneous Operation Modes Allowed with Four Planes IF ONE Read Read PARTITION IS: Array ID/OTP Read Array X X Read ID/OTP X X Read Status X X Read Query X X Word Program X X Page Buffer X ...
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BLOCK NUMBER ADDRESS RANGE 134 3F8000H - 3FFFFFH 32K-WORD 133 3F0000H - 3F7FFFH 32K-WORD 132 3E8000H - 3EFFFFH 32K-WORD 131 3E0000H - 3E7FFFH 32K-WORD 130 32K-WORD 3D8000H - 3DFFFFH 129 32K-WORD 3D0000H - 3D7FFFH 128 32K-WORD 3C8000H - 3CFFFFH 127 ...
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Table 3. Identifier Codes and OTP Address for Read Operation Manufacturer Code Manufacturer Code Device Code Bottom Parameter Device Code Block Lock Configuration Block is Unlocked Code Block is Locked Block is not Locked-Down Block is Locked-Down Device Configuration Code ...
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LHF64FD5 [ 000088H Customer Programmable Area 000085H 000084H Factory Programmed Area 000081H Reserved for Future Implementation 000080H (DQ -DQ 15 Customer Programmable Area Lock Bit (DQ Factory Programmed Area Lock Bit (DQ Figure 3. OTP Block ...
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Mode Notes RST# Read Array Output Disable V IH Standby V IH Reset Read Identifier Codes/OTP V Read Query 6,7 IH Write 4,5 NOTES: 1. Refer to DC Characteristics. ...
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Command Read Array Read Identifier Codes/OTP Read Query Read Status Register Clear Status Register Block Erase Full Chip Erase Program Page Buffer Program Block Erase and (Page Buffer) Program Suspend Block Erase and (Page Buffer) Program Resume Set Block Lock ...
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... Following the Clear Block Lock Bit command, block which is not locked-down is unlocked when WP WP lock-down bit is disabled and the selected block is unlocked regardless of lock-down configuration. IH 11. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used. LHF64FD5 11 ...
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Table 7. Functions of Block Lock Current State (1) State WP [000 ( [001] [011 [100 ( [101] ( [110] [111 NOTES ...
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Table 9. Block Locking State Transitions upon WP# Transition Current State Previous State State - [000] - [001] (2) [110] [011] (2) Other than [110] - [100] - [101] - [110] - [111] NOTES: 1. "WP#=0 1" means that WP# ...
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WSMS BESS BEFCES 7 6 SR.15 - SR.8 = RESERVED FOR FUTURE ENHANCEMENTS (R) SR.7 = WRITE STATE MACHINE STATUS (WSMS Ready 0 = Busy SR.6 = BLOCK ERASE SUSPEND STATUS (BESS ...
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SMS XSR.15-8 = RESERVED FOR FUTURE ENHANCEMENTS (R) XSR.7 = STATE MACHINE STATUS (SMS Page Buffer Program available 0 = Page Buffer Program not available XSR.6-0 = RESERVED FOR FUTURE ENHANCEMENTS ...
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PCR.15-11 = RESERVED FOR FUTURE ENHANCEMENTS (R) PCR.10-8 = PARTITION CONFIGURATION (PC2-0) 000 = No partitioning. Dual Work is not allowed. 001 = Plane1-3 are merged into one partition. (default in a ...
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Electrical Specifications 1.1 Absolute Maximum Ratings Operating Temperature During Read, Erase and Program ...- +85 C Storage Temperature During under Bias............................... - +85 C During non Bias................................ - +125 C Voltage On Any ...
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Capacitance ( f=1MHz) A Parameter Symbol Input Capacitance Output Capacitance NOTE: 1. Sampled, not 100% tested. 1.2.2 AC Input/Output Test Conditions V CCQ INPUT 0.0 AC test inputs are driven at V Input timing begins, ...
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DC Characteristics Symbol Parameter I Input Load Current LI I Output Leakage Current Standby Current CCS Automatic Power Savings Current CCAS Reset Power-Down Current CCD CC Average V Read CC ...
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Symbol Parameter V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH V Lockout during Normal PP V PPLK Operations V during Block Erase, Full Chip PP V Erase, (Page ...
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AC Characteristics - Read-Only Operations Symbol t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV t Page Address Access Time APA t OE# to Output Delay GLQV t RST# High to ...
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(A) (A) 21-0 20 EHEL V IH CE# ( OE# ( (W) WE (D/Q) 15 ...
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(A) (A) 21-3 20 (A) 2 (E) CE OE# ( WE# ( High ...
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(A) (A) 21-3 20 (A) 2 (E) CE OE# ( WE# ( GLQX t ELQX V ...
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AC Characteristics - Write Operations Symbol t Write Cycle Time AVAV RST# High Recovery to WE# (CE#) Going Low PHWL PHEL CE# (WE#) Setup to WE# (CE#) Going Low ELWL WLEL t (t ...
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NOTE (A) (A) 20-0 21 CE# ( ELWL WLEL V IH OE# ( PHWL PHEL V IH WE# ( ...
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Reset Operations V IH RST# ( High (D/Q) 15 RST# ( High (D/Q) 15 (min GND V ...
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Block Erase, Full Chip Erase, (Page Buffer) Program and OTP Program Performance Symbol Parameter 4K-Word Parameter Block t WPB Program Time 32K-Word Main Block t WMB Program Time t / WHQV1 Word Program Time t EHQV1 t / WHOV1 ...
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... Related Document Information Document No. FUM00701 NOTE: 1. International customers should contact their local SHARP or distribution sales offices. LHF64FD5 (1) Document Name LH28F640BF series Appendix 29 Rev. 2.44 ...
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A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate ...
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A-1.1.1 Rise and Fall Time Symbol t V Rise Time Input Signal Rise Time R t Input Signal Fall Time F NOTES: 1. Sampled, not 100% tested. 2. This specification is applied for not only the device ...
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A-1.2 Glitch Noises Do not input the glitch noises which are below V as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a). Input Signal V (Min (Max.) IL Input Signal (a) ...
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... A-2 RELATED DOCUMENT INFORMATION Document No. AP-001-SD-E AP-006-PT-E AP-007-SW-E NOTE: 1. International customers should contact their local SHARP or distribution sales office. (1) Document Name Flash Memory Family Software Drivers Data Protection Method of SHARP Flash Memory RP#, V Electric Potential Switching Circuit PP iv Rev. 1.10 ...
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A-3 STATUS REGISTER READ OPERATIONS If AC timing for reading the status register described in specifications is not satisfied, a system processor can check the status register bit SR.15 instead of SR.7 to determine when the erase or program operation ...