TE28F640J3A-150 Intel Corporation, TE28F640J3A-150 Datasheet - Page 24

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TE28F640J3A-150

Manufacturer Part Number
TE28F640J3A-150
Description
TE28F640J3A-150Intel StrataFlash Memory (J3)
Manufacturer
Intel Corporation
Datasheet
256-Mbit J3 (x8/x16)
NOTES:
1. CE
low is defined as the last edge of CE0, CE1, or CE2 that enables the device. CE
X
first edge of CE0, CE1, or CE2 that disables the device (see
2. When reading the flash array a faster t
Register reads, query reads, or device identifier reads).
Figure 10. 4-Word Page Mode Read Waveform
A[MAX:3] [A]
A[2:1] [A]
CEx [E]
OE# [G]
WE# [W]
R6
R7
D[15:0] [Q]
R5
RP# [P]
NOTE: CE
low is defined as the last edge of CE0, CE1, or CE2 that enables the device. CE
X
the first edge of CE0, CE1, or CE2 that disables the device (see
24
(R16) applies. For non-array reads, R4 applies (i.e.: Status
GLQV
R1
R1
R2
00
01
R3
R4
R10
R15
1
2
high is defined at the
X
Table
13).
10
11
R8
R10
R9
3
4
high is defined at
X
Table
13).
Datasheet
0606_16

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