TE28F640J3A-150

Manufacturer Part NumberTE28F640J3A-150
DescriptionTE28F640J3A-150Intel StrataFlash Memory (J3)
ManufacturerIntel Corporation
TE28F640J3A-150 datasheet
 
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Page 26/72:

Write Operations

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256-Mbit J3 (x8/x16)
7.2

Write Operations

Table 9.

Write Operations

Versions
#
Symbol
W1
t
(t
)
RP# High Recovery to WE# (CE
PHWL
PHEL
W2
t
(t
)
CE
(WE#) Low to WE# (CE
ELWL
WLEL
X
W3
t
Write Pulse Width
WP
W4
t
(t
)
Data Setup to WE# (CE
DVWH
DVEH
W5
t
(t
)
Address Setup to WE# (CE
AVWH
AVEH
W6
t
(t
)
CE
(WE#) Hold from WE# (CE
WHEH
EHWH
X
W7
t
(t
)
Data Hold from WE# (CE
WHDX
EHDX
W8
t
(t
)
Address Hold from WE# (CE
WHAX
EHAX
W9
t
Write Pulse Width High
WPH
W11
t
(t
)
V
Setup to WE# (CE
VPWH
VPEH
PEN
W12
t
(t
)
Write Recovery before Read
WHGL
EHGL
W13
t
(t
)
WE# (CE
WHRL
EHRL
X
W15
t
V
Hold from Valid SRD, STS Going High
QVVL
PEN
NOTES:
CE
low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CE
X
or CE2 that disables the device (see
Table
13).
1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as
during read-only operations. Refer to AC Characteristics–Read-Only Operations.
2. A write operation can be initiated and terminated with either CE
3. Sampled, not 100% tested.
4. Write pulse width (t
) is defined from CE
WP
high (whichever goes high first). Hence, t
5. Refer to
Table 14
for valid A
and D
IN
6. Write pulse width high (t
) is defined from CE
WPH
going low (whichever goes low first). Hence, t
7. For array access, t
is required in addition to t
AVQV
8. STS timings are based on STS configured in its RY/BY# default mode.
9. V
should be held at V
until determination of block erase, program, or lock-bit configuration success
PEN
PENH
(SR[1,3,4:5] = 0).
26
Parameter
) Going Low
X
) Going Low
X
) Going High
X
) Going High
X
) High
X
) High
X
) High
X
) Going High
X
) High to STS Going Low
high is defined at the first edge of CE0, CE1,
X
or WE#.
X
or WE# going low (whichever goes low last) to CE
X
= t
= t
= t
= t
WP
WLWH
ELEH
WLEH
ELWH
for block erase, program, or lock-bit configuration.
IN
or WE# going high (whichever goes high first) to CE
X
= t
= t
= t
= t
WPH
WHWL
EHEL
WHEL
for any accesses after a write.
WHGL
Valid for All
Speeds
Unit
Notes
Min
Max
1
µs
0
ns
70
ns
50
ns
55
ns
0
ns
0
ns
0
ns
30
ns
0
ns
35
ns
500
ns
0
ns
1,2,3,8,9
or WE# going
X
.
or WE#
X
.
EHWL
Datasheet
1,2,3
1,2,4
1,2,4
1,2,5
1,2,5
1,2,
1,2,
1,2,
1,2,6
1,2,3
1,2,7
1,2,8