TE28F640J3A-150

Manufacturer Part NumberTE28F640J3A-150
DescriptionTE28F640J3A-150Intel StrataFlash Memory (J3)
ManufacturerIntel Corporation
TE28F640J3A-150 datasheet
 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Page 31
32
Page 32
33
Page 33
34
Page 34
35
Page 35
36
Page 36
37
Page 37
38
Page 38
39
Page 39
40
Page 40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Page 33/72:

Bus Read Operation

Download datasheet (552Kb)Embed
PrevNext
Table 13. Chip Enable Truth Table
CE2
V
IL
V
IL
V
IL
V
IL
V
IH
V
IH
V
IH
V
IH
NOTE: For single-chip applications, CE2 and CE1 can be connected to V
9.1.1

Bus Read Operation

To perform a bus read operation, CEx (refer to
CEx is the device-select control; when active, it enables the flash memory device. OE# is the data-
output control; when active, the addressed flash memory data is driven onto the I/O bus. For all
read states, WE# and RP# must be de-asserted. See
Refer to
Section 10.0, “Read Operations” on page 37
and refer to
Section 14.0, “Special Modes” on page 50
states.
9.1.2
Bus Write Operation
Writing commands to the Command User Interface enables various modes of operation, including
the reading of array data, CFI data, identifier codes, inspection and clearing of the Status Register,
and, when V
= V
PEN
The Block Erase command requires appropriate command data and an address within the block to
be erased. The Byte/Word Program command requires the command and address of the location to
be written. Set Block Lock-Bit commands require the command and block within the device to be
locked. The Clear Block Lock-Bits command requires the command and address within the device.
The CUI does not occupy an addressable memory location. It is written when the device is enabled
and WE# is active. The address and data needed to execute a command are latched on the rising
edge of WE# or the first edge of CE0, CE1, or CE2 that disables the device (see
page
33). Standard microprocessor write timings are used.
9.1.3
Output Disable
With CEx asserted, and OE# at a logic-high level (V
signals D[15:0] are placed in a high-impedance state.
Datasheet
CE1
CE0
V
V
IL
IL
V
V
IL
IH
V
V
IH
IL
V
V
IH
IH
V
V
IL
IL
V
V
IL
IH
V
V
IH
IL
V
V
IH
IH
Table 13 on page
Section 7.1, “Read Operations” on page
for details on reading from the flash array,
for details regarding all other available read
, block erasure, program, and lock-bit configuration.
PENH
), the device outputs are disabled. Output
IH
256-Mbit J3 (x8/x16)
DEVICE
Enabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Disabled
.
IL
33) and OE# must be asserted.
22.
Table 13 on
33