TE28F640J3A-150

Manufacturer Part NumberTE28F640J3A-150
DescriptionTE28F640J3A-150Intel StrataFlash Memory (J3)
ManufacturerIntel Corporation
TE28F640J3A-150 datasheet
 
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Page 51/72:

STS Configuration Coding Definitions

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Table 22. STS Configuration Coding Definitions
D7
D6
D[1:0] = STS Configuration Codes
10 = pulse on Program Complete
11 = pulse on Erase or Program
Complete
NOTES:
1. When configured in one of the pulse modes, STS pulses low with a typical pulse width of 250 ns.
2. An invalid configuration code will result in both SR.4 and SR.5 being set.
Datasheet
D5
D4
D3
Reserved
Used to generate a system interrupt pulse when any flash device in
an array has completed a program operation. Provides highest
performance for servicing continuous buffer write operations.
Used to generate system interrupts to trigger servicing of flash arrays
when either erase or program operations are completed, when a
common interrupt service routine is desired.
256-Mbit J3 (x8/x16)
D2
D1
D0
Pulse on
Pulse on
Program
Erase
Complete
Complete
(1)
(1)
Notes
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