TE28F640J3A-150 Clear Lock-bit Flowchart - Intel Corporation

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TE28F640J3A-150

Manufacturer Part Number
TE28F640J3A-150
Description
TE28F640J3A-150Intel StrataFlash Memory (J3)
Manufacturer
Intel Corporation
Datasheet
256-Mbit J3 (x8/x16)
Figure 25. Clear Lock-Bit Flowchart
Start
Write 60H
Write D0H
Read Status Register
SR.7 =
1
Full Status
Check if Desired
Clear Block Lock-Bits
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
SR.3 =
0
SR.4,5 =
0
SR.5 =
0
Clear Block Lock-Bits
Successful
66
Bus
Operation
Write
Write
Read
Standby
0
Write FFH after the clear lock-bits operation to place device in read
array mode.
Bus
Operation
Standby
1
Voltage Range Error
Standby
1
Command Sequence
Standby
Error
SR.5, SR.4, and SR.3 are only cleared by the Clear Status Register
command.
1
Clear Block Lock-Bits
If an error is detected, clear the status register before attempting retry
Error
or other error recovery.
Command
Comments
Clear Block
Data = 60H
Lock-Bits Setup
Addr = X
Clear Block or
Data = D0H
Lock-Bits Confirm
Addr = X
Status Register Data
Check SR.7
1 = WSM Ready
0 = WSM Busy
Command
Comments
Check SR.3
1 = Programming Voltage Error
Detect
Check SR.4, 5
Both 1 = Command Sequence
Error
Check SR.5
1 = Clear Block Lock-Bits Error
Datasheet

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