TE28F640J3C-120 Intel Corporation, TE28F640J3C-120 Datasheet

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TE28F640J3C-120

Manufacturer Part Number
TE28F640J3C-120
Description
TE28F640J3C-120Intel StrataFlash Memory (J3)
Manufacturer
Intel Corporation
Datasheet

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Intel StrataFlash
256-Mbit (x8/x16)
Product Features
Capitalizing on Intel’s 0.25 and 0.18 micron, two-bit-per-cell technology, the Intel StrataFlash
device provides 2X the bits in 1X the space, with new features for mainstream performance. Offered in 256-
Mbit (32-Mbyte), 128-Mbit (16-Mbyte), 64-Mbit, and 32-Mbit densities, the J3 device brings reliable, two-bit-
per-cell storage technology to the flash market segment. Benefits include more density in less space, high-speed
interface, lowest cost-per-bit NOR device, support for code and data storage, and easy migration to future
devices.
Using the same NOR-based ETOX™ technology as Intel’s one-bit-per-cell products, the J3 device takes
advantage of over one billion units of flash manufacturing experience since 1987. As a result, J3 components
are ideal for code and data applications where high density and low cost are required. Examples include
networking, telecommunications, digital set top boxes, audio recording, and digital imaging.
By applying FlashFile™ memory family pinouts, J3 memory components allow easy design migrations from
existing Word-Wide FlashFile memory (28F160S3 and 28F320S3), and first generation Intel StrataFlash
memory (28F640J5 and 28F320J5) devices.
J3 memory components deliver a new generation of forward-compatible software support. By using the
Common Flash Interface (CFI) and the Scalable Command Set (SCS), customers can take advantage of density
upgrades and optimized write capabilities of future Intel StrataFlash
0.18 micron ETOX™ VII (J3C) and 0.25 micron ETOX™ VI (J3A) process technology, the J3 memory device
provides the highest levels of quality and reliability.
Notice: This document contains information on new products in production. The specifications are
subject to change without notice. Verify with your local Intel sales office that you have the latest
datasheet before finalizing a design.
Performance
Software
Security
— 110/115/120/150 ns Initial Access Speed
— 125 ns Initial Access Speed (256 Mbit
— 25 ns Asynchronous Page mode Reads
— 30 ns Asynchronous Page mode Reads
— 32-Byte Write Buffer
— Program and Erase suspend support
— Flash Data Integrator (FDI), Common
— 128-bit Protection Register
— Absolute Protection with V
— Individual Block Locking
— Block Erase/Program Lockout during
—64-bit Unique Device Identifier
—64-bit User Programmable OTP Cells
density only)
(256Mbit density only)
Flash Interface (CFI) Compatible
Power Transitions
—6.8 µs per byte effective
programming time
PEN
®
= GND
Memory (J3)
Architecture
Quality and Reliability
Packaging and Voltage
— Multi-Level Cell Technology: High
— High-Density Symmetrical 128-Kbyte
— Operating Temperature:
— 100K Minimum Erase Cycles per Block
— 0.18 µm ETOX™ VII Process (J3C)
— 0.25 µm ETOX™ VI Process (J3A)
— 56-Lead TSOP Package
— 64-Ball Intel
— Lead-free packages available
— 48-Ball Intel
— V
— V
Density at Low Cost
Blocks
—256 Mbit (256 Blocks) (0.18µm only)
—128 Mbit (128 Blocks)
—64 Mbit (64 Blocks)
—32 Mbit (32 Blocks)
-40 °C to +85 °C
64 Mbit) (x16 only)
CC
CCQ
®
memory devices. Manufactured on Intel
= 2.7 V to 3.6 V
= 2.7 V to 3.6 V
®
®
VF BGA Package (32 and
Easy BGA Package
Order Number: 290667-021
Datasheet
®
Memory (J3)
March 2005
®
®

Related parts for TE28F640J3C-120

TE28F640J3C-120 Summary of contents

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Intel StrataFlash 256-Mbit (x8/x16) Product Features Performance — 110/115/120/150 ns Initial Access Speed — 125 ns Initial Access Speed (256 Mbit density only) — Asynchronous Page mode Reads — Asynchronous Page mode Reads (256Mbit ...

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... Intel's website at http://www.intel.com. Copyright © 2005, Intel Corporation. All rights reserved. Intel and ETOX are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. ...

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Contents 1.0 Introduction....................................................................................................................................7 1.1 Nomenclature .......................................................................................................................7 1.2 Conventions..........................................................................................................................7 2.0 Functional Overview .....................................................................................................................8 2.1 Block Diagram ......................................................................................................................9 2.2 Memory Map .......................................................................................................................10 3.0 Package Information ...................................................................................................................11 3.1 56-Lead TSOP Package .....................................................................................................11 3.2 Easy BGA (J3) Package .....................................................................................................12 3.3 VF-BGA (J3) Package ........................................................................................................13 ...

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Contents 9.2 Device Commands ............................................................................................................. 35 10.0 Read Operations.......................................................................................................................... 37 10.1 Read Array.......................................................................................................................... 37 10.1.1 Asynchronous Page Mode Read ........................................................................... 37 10.1.2 Enhanced Configuration Register (ECR)............................................................... 38 10.2 Read Identifier Codes ......................................................................................................... 39 10.2.1 Read Status Register............................................................................................. 39 10.3 Read ...

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Revision History Date of Version Revision 07/07/99 -001 08/03/99 -002 09/07/99 -003 12/16/99 -004 03/16/00 -005 06/26/00 -006 2/15/01 -007 04/13/01 -008 Datasheet Description Original Version A –A indicated on block diagram 0 2 Changed Minimum Block Erase time,I OL ...

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Contents Date of Version Revision 07/27/01 -009 10/31/01 -010 03/21/02 -011 12/12/02 -012 01/24/03 -013 12/09/03 -014 1/3/04 -015 1/23/04 -016 1/23/04 -016 5/19/04 -018 7/7/04 -019 11/23/04 -020 3/24/05 -021 6 Description ® Added Figure 4, 3 Volt Intel ...

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Introduction This document describes the Intel StrataFlash device features, operations, and specifications. 1.1 Nomenclature AMIN: AMIN = A0 for x8 AMIN = A1 for x16 AMAX: 32 Mbit 64 Mbit 128 Mbit 256 Mbit Block: A group of flash ...

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J3 (x8/x16) 2.0 Functional Overview The Intel StrataFlash 16Mwords (256-Mbit, available on the 0.18µm lithography process only), 16 Mbytes or 8 Mwords (128-Mbit), 8 Mbytes or 4 Mwords (64-Mbit), and 4 Mbytes or 2 Mwords (32-Mbit). These devices can ...

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Additionally, the configuration command allows the STS signal to be configured to pulse on completion of programming and/or block erases. Three CE signals are ...

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J3 (x8/x16) 2.2 Memory Map Figure 2. Intel StrataFlash A[24-0]: 256 Mbit A [23-0]:128 Mbit A [22-0]: 64 Mbit A [21-0]: 32 Mbit 1FFFFFF 128-Kbyte Block 1FE0000 0FFFFFF 128-Kbyte Block 0FE0000 07FFFFF 128-Kbyte Block 07E0000 03FFFFF 128-Kbyte Block 03E0000 ...

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Package Information 3.1 56-Lead TSOP Package Figure 3. 56-Lead TSOP Package Drawing and Specifications Z Pin 1 See Detail A Detail A Table 1. 56-Lead TSOP Dimension Table Sym Package Height A Standoff A 1 Package Body Thickness A ...

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J3 (x8/x16) 3.2 Easy BGA (J3) Package Figure 4. Intel StrataFlash Ball A1 Corner Top View - Ball side down A1 A2 Table 2. ...

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VF-BGA (J3) Package Figure 5. Intel StrataFlash ...

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J3 (x8/x16) 4.0 Ballout and Signal Descriptions ® Intel StrataFlash memory is available in three package types. Each density of the J3C is supported on both 64-ball Easy BGA and 56-lead Thin Small Outline Package (TSOP) packages. A 48-ball ...

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TSOP (32/64/128/256 Mbit) Figure 7. Intel StrataFlash 28F160S3 28F320J5 RP# ...

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J3 (x8/x16) 4.4 Signal Descriptions Table 3 describes active signals used. Table 3. Signal Descriptions (Sheet Symbol Type BYTE-SELECT ADDRESS: Selects between high and low byte when the device mode. A0 Input This ...

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Table 3. Signal Descriptions (Sheet Symbol Type GND Supply GROUND: Do not float any ground signals. NC — NO CONNECT: Lead is not internally connected; it may be driven or floated. RESERVED for FUTURE USE: Balls designated ...

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J3 (x8/x16) 5.0 Maximum Ratings and Operating Conditions 5.1 Absolute Maximum Ratings This datasheet contains information on new products in production. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have ...

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Electrical Specifications 6.1 DC Current Characteristics Table 6. DC Current Characteristics (Sheet VCCQ VCC Symbol Parameter I Input and V Load Current LI PEN I Output Leakage Current Standby Current CCS CC I ...

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J3 (x8/x16) Table 6. DC Current Characteristics (Sheet VCCQ VCC Symbol Parameter V Block Erase or Clear CC I CCE Block Lock-Bits Current V Program Suspend CCWS Block Erase Suspend I CCES Current ...

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Table 7. DC Voltage Characteristics Symbol V during Block Erase, PEN V PENH Program, or Lock-Bit Operations V V Lockout Voltage LKO CC NOTES: 1. Includes STS. 2. Sampled, not 100% tested. 3. Block erases, programming, and lock-bit configurations are ...

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J3 (x8/x16) 7.0 AC Characteristics 7.1 Read Operations Table 8. Read Operations (Sheet Asynchronous Specifications (All units in ns unless otherwise noted) Speed Bin # Sym Parameter Density 32 Mbit 64 Mbit Read/Write R1 t AVAV ...

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Table 8. Read Operations (Sheet Asynchronous Specifications (All units in ns unless otherwise noted) Speed Bin # Sym Parameter Density t FLQV/ R12 BYTE# to Output Delay t FHQV R13 t BYTE# to Output in High Z ...

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J3 (x8/x16) NOTES low is defined as the last edge of CE0, CE1, or CE2 that enables the device first edge of CE0, CE1, or CE2 that disables the device (see 2. When reading the ...

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Figure 11. 8-word Asynchronous Page Mode Read A[MAX:4] [A] A[3:1] [A] CEx [E] OE# [G] WE# [W] D[15:0] [Q] RP# [P] BYTE# NOTES low is defined as the last edge of CE0, CE1, or CE2 that enables the ...

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J3 (x8/x16) 7.2 Write Operations Table 9. Write Operations Versions # Symbol RP# High Recovery to WE# (CE PHWL PHEL (WE#) Low to WE# (CE ELWL WLEL ...

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Block Erase, Program, and Lock-Bit Configuration Performance Table 10. Configuration Performance # Sym Write Buffer Byte Program Time W16 (Time to Program 32 bytes/16 words) t WHQV3 W16 Byte Program Time (Using Word/Byte Program Command) t EHQV3 Block Program ...

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J3 (x8/x16) Figure 12. Asynchronous Write Waveform ADDRESS [A] CEx (WE#) [E (W)] W2 WE# (CEx) [W (E)] OE# [G] DATA [D/Q] STS[R] W1 RP# [P] VPEN [V] Figure 13. Asynchronous Write to Read Waveform Address [A] CE# [E] ...

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Reset Operation Figure 14. AC Waveform for Reset Operation V IH STS ( RP# ( NOTE: STS is shown in its default mode (RY/BY#). Table 11. Reset Specifications # Sym RP# Pulse Low ...

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J3 (x8/x16) Figure 16. Transient Equivalent Testing Load Circuit NOTE: C Includes Jig Capacitance. L Test Configuration 2.7 V−3.6 V CCQ CC 7.6 Capacitance T = +25 ° MHz A Symbol C ...

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Power and Reset Specifications This section provides an overview of system level considerations for the Intel StrataFlash memory family device. This section provides a brief description of power-up, power-down, decoupling and reset design considerations. 8.1 Power-Up/Down Characteristics In order ...

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J3 (x8/x16) 9.0 Bus Operations This section provides an overview of device bus operations. The on-chip Write State Machine (WSM) manages all erase and program algorithms. The system CPU provides control of all in- system read, write, and erase ...

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Table 13. Chip Enable Truth Table CE2 NOTE: For single-chip applications, CE2 and CE1 can be connected to V 9.1.1 Bus Read Operation To ...

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J3 (x8/x16) 9.1.4 Standby CE0, CE1, and CE2 can disable the device (see This manipulation of CEx substantially reduces device power consumption. D[15:0] outputs are placed in a high-impedance state independent of OE#. If deselected during block erase, program, ...

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Device Commands voltage ≤ V When the V PEN codes, or blocks are enabled. Placing V and lock-bit configuration operations. Device operations are selected by writing specific commands into the CUI. commands. Table 14. Command Bus-Cycle Definitions (Sheet 1 ...

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J3 (x8/x16) Table 14. Command Bus-Cycle Definitions (Sheet Scalable or Basic Command Command (2) Set Clear Block Lock-Bits SCS Protection Program NOTES: 1. Commands other than those shown above are reserved by Intel for future device ...

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Read Operations The device supports four types of read modes: Read Array, Read Identifier, Read Status, and CFI query. Upon power-up or return from reset, the device defaults to read array mode. To change the device’s read mode, the ...

Page 38

J3 (x8/x16) To perform a page mode read after any other operation, the Read Array command must be issued to read from the flash array. Asynchronous page mode reads are permitted in all blocks and are used to access ...

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Read Identifier Codes The Read identifier codes operation outputs the manufacturer code, device-code, and the block lock configuration codes for each block (See details on issuing the Read Device Identifier command). Page-mode reads are not supported in this read ...

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J3 (x8/x16) Table 18. Status Register Definitions WSMS ESS ECLBS bit 7 bit 6 bit 5 High Z When Status Register Bits Busy? SR.7 = WRITE STATE MACHINE STATUS Ready 0 = Busy Yes SR.6 = ...

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Read Query/CFI The query register contains an assortment of flash product information such as block size, density, allowable command sets, electrical specifications and other product information. The data contained in this register conforms to the Common Flash Interface (CFI) ...

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J3 (x8/x16) 11.0 Programming Operations The device supports two different programming methods: word programming, and write-buffer programming. Successful programming requires the addressed block to be unlocked. An attempt to program a locked block will result in the operation aborting, ...

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After the final buffer data is given, a Write Confirm command is issued. This initiates the WSM (Write State Machine) to begin copying the buffer data to the flash array command other than Write Confirm is written to ...

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J3 (x8/x16) 12.0 Erase Operations Flash erasing is performed on a block basis; therefore, only one block can be erased at a time. Once a block is erased, all bits within that block will read as a logic level ...

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The only other valid commands while block erase is suspended are Read Query, Read Status Register, Clear Status Register, Configure, and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue ...

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J3 (x8/x16) 13.0 Security Modes This device offers both hardware and software security features. Block lock operations, PRs, and VPEN allow the user to implement various levels of data protection. The following section describes security features in detail. Other ...

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This two-step sequence of setup followed by execution ensures that block lock-bits are not accidentally cleared. An invalid Clear Block Lock-Bits command sequence will result in SR.4 and SR.5 being set. Also, a reliable clear block lock-bits operation can only ...

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J3 (x8/x16) Figure 17. Protection Register Memory Map NOTE not used in x16 mode when accessing the Protection Register map (See addressing). For x8 mode A0 is used (See Table 20. Word-Wide Protection Register Addressing Word Use ...

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Table 21. Byte-Wide Protection Register Addressing (Sheet Factory 7 Factory 8 User 9 User A User B User C User D User E User F User NOTE: All address lines not specified in the above table ...

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J3 (x8/x16) 14.0 Special Modes This section describes how to read the status, ID, and CFI registers. This section also details how to configure the STS signal. 14.1 Set Read Configuration Register Command This command is no longer supported ...

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Table 22. STS Configuration Coding Definitions D7 D6 D[1:0] = STS Configuration Codes 10 = pulse on Program Complete 11 = pulse on Erase or Program Complete NOTES: 1. When configured in one of the pulse modes, STS pulses low ...

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J3 (x8/x16) Appendix A Common Flash Interface The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake which allows specific vendor-specified software algorithms to be used for entire families of devices. This allows device independent, ...

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Table 23. Summary of Query Structure Output as a Function of Device and Mode Device Query start location in Type/ maximum device bus Mode width addresses x16 device x16 mode x16 device x8 mode NOTE: 1. The system must drive ...

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J3 (x8/x16) Table 25. Query Structure Offset 00h 01h (BA+2)h (2) Block Status Register 04-0Fh Reserved 10h CFI Query Identification String 1Bh System Interface Information 27h Device Geometry Definition Primary Intel-Specific Extended (3) P Query Table NOTES: 1. Refer ...

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Table 27. CFI Identification (Sheet Offset Length 0000h means no second vendor-specified algorithm exists 19h 2 Secondary algorithm Extended Query Table address. 0000h means none exists A.5 System Interface Information The following device information can optimize system ...

Page 56

J3 (x8/x16) Table 29. Device Geometry Definition (Sheet Offset Length Number of erase block regions within device means no erase blocking; the device erases in “bulk” specifies the number of ...

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Table 30. Primary Vendor-Specific Extended Query (Sheet (1) Offset Length P = 31h (P+5)h (P+6)h 4 (P+7)h (P+8)h (P+9)h 1 (P+A)h 2 (P+B)h (P+C)h 1 (P+D)h 1 NOTE: 1. Future devices may not support the described “Legacy ...

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J3 (x8/x16) Table 31. Protection Register Information (1) Offset Length P = 31h (P+E)h 1 (P+F)h (P+10)h 4 (P+11)h (P+12)h NOTE: 1. The variable pointer which is defined at CFI offset 15h. Table 32. Burst Read ...

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Appendix B Flow Charts Figure 18. Write to Buffer Flowchart Datasheet Start Setup - Write 0xE8 - Block Address Check Buffer Status - Perform read operation - Read Ready Status on signal SR7 No SR7 = 1? Yes Word Count ...

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J3 (x8/x16) Figure 19. Status Register Flowchart Start Command Cycle - Issue Status Register Command - Address = any dev ice address - Data = 0x70 Data Cycle - Read Status Register SR[7:0] SR7 = ' ...

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Figure 20. Byte/Word Program Flowchart Start Write 40H, Address Write Data and Address Read Status Register SR Full Status Check if Desired Byte/Word Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR ...

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J3 (x8/x16) Figure 21. Program Suspend/Resume Flowchart Start Write B0H Read Status Register SR SR Write FFH Read Data Array Done Reading Yes Write D0H Programming Resumed 62 Bus Operation Write Read Standby Standby 0 ...

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Figure 22. Block Erase Flowchart Start Issue Single Block Erase Command 20H, Block Address Write Confirm D0H Block Address Read Status Register SR Full Status Check if Desired Erase Flash Block(s) Complete Datasheet Bus Operation Write Write (Note ...

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J3 (x8/x16) Figure 23. Block Erase Suspend/Resume Flowchart Start Write B0H Read Status Register SR.7 = SR.6 = Read Read or Program? Read Array Data Done? Write D0H Block Erase Resumed 64 Operation Standby Standby Block ...

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Figure 24. Set Block Lock-Bit Flowchart Start Write 60H, Block Address Write 01H, Block Address Read Status Register SR Full Status Check if Desired Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3 ...

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J3 (x8/x16) Figure 25. Clear Lock-Bit Flowchart Start Write 60H Write D0H Read Status Register SR Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3 = ...

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Figure 26. Protection Register Programming Flowchart Start Write C0H (Protection Reg. Program Setup) Write Protect. Register Address/Data Read Status Register SR Yes Full Status Check if Desired Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See ...

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J3 (x8/x16) Appendix C Design Considerations C.1 Three-Line Output Control The device will often be used in large memory arrays. Intel provides five control inputs (CE0, CE1, CE2, OE#, and RP#) to accommodate multiple memory connections. This control provides ...

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C RP# Transitions CC PEN Block erase, program, and lock-bit configuration are not guaranteed if V the specified operating ranges, or RP# ≠ V program, or lock-bit configuration, STS (in default mode) will remain low for ...

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J3 (x8/x16) Appendix D Additional Information Order Number 298130 298136 297833 290737 292280 292237 290606 297859 292222 292221 292218 292204 253418 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact ...

Page 71

... Mbit) NOTE: 1. Speeds are for either the standard asynchronous read access times or for the first access of a page-mode read sequence. VALID COMBINATIONS 56-Lead TSOP E28F320J3A-110 E28F640J3A-120 E28F128J3A-150 TE28F320J3C-110 TE28F640J3C-115 TE28F640J3C-120 TE28F128J3C-120 TE28F128J3C-150 TE28F256J3C-125 56-Lead Pb-Free TSOP JS28F256J3C125 JS28F128J3C120 JS28F640J3C115 JS28F320J3C110 Datasheet ...

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J3 (x8/x16) 72 Datasheet ...

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