TE28F640J3C-150

Manufacturer Part NumberTE28F640J3C-150
DescriptionTE28F640J3C-150Intel StrataFlash Memory (J3)
ManufacturerIntel Corporation
TE28F640J3C-150 datasheet
 
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Page 32/72:

Bus Operations

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256-Mbit J3 (x8/x16)
9.0

Bus Operations

This section provides an overview of device bus operations. The on-chip Write State Machine
(WSM) manages all erase and program algorithms. The system CPU provides control of all in-
system read, write, and erase operations of the device via the system bus.
Device commands are written to the CUI to control all of the flash memory device’s operations.
The CUI does not occupy an addressable memory location; it’s the mechanism through which the
flash device is controlled.
9.1
Bus Operations Overview
The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash
memory conform to standard microprocessor bus cycles.
Table 12. Bus Operations
Mode
RP#
CE[2:0]
Read Array
V
Enabled
IH
Output Disable
V
Enabled
IH
Standby
V
Disabled
IH
Reset/Power-Down
V
X
IL
Mode
Read Identifier Codes
V
Enabled
IH
Read Query
V
Enabled
IH
Read Status (WSM off)
V
Enabled
IH
Read Status (WSM on)
V
Enabled
IH
Write
V
Enabled
IH
NOTES:
1. See
Table 13 on page 33
for valid CE configurations.
2. OE# and WE# should never be enabled simultaneously.
3. D refers to D[7:0] if BYTE# is low and D[15:0] if BYTE# is high.
4. Refer to DC Characteristics. When V
5. X can be V
or V
for control and address signals, and V
IL
IH
V
voltages.
PENH
6. In default mode, STS is V
when the WSM is executing internal block erase, program, or lock-bit configuration algorithms. It
OL
is V
when the WSM is not busy, in block erase suspend mode (with programming inactive), program suspend mode, or
OH
reset/power-down mode.
7. High Z will be V
with an external pull-up resistor.
OH
8. See
Section 10.2, “Read Identifier Codes” on page 39
9. See
Section 10.3, “Read Query/CFI” on page 41
10.Command writes involving block erase, program, or lock-bit configuration are reliably executed when V
is within specification.
32
(1)
(2)
(2)
OE#
WE#
Address
VPEN
V
V
X
IL
IH
V
V
X
IH
IH
X
X
X
X
X
X
See
V
V
IL
IH
Table 17
See
V
V
Table
IL
IH
10.3
V
V
X
IL
IH
V
V
X
IL
IH
V
V
X
V
IH
IL
≤ V
, memory contents can be read, but not altered.
PEN
PENLK
or V
for V
PENLK
PENH
for read identifier code data.
for read query data.
STS
(3)
Data
(default
Notes
mode)
(7)
X
D
High Z
OUT
X
High Z
X
X
High Z
X
(7)
X
High Z
High Z
(7)
X
Note 8
High Z
(7)
X
Note 9
High Z
X
D
OUT
D7 = D
OUT
X
D[15:8] = High Z
D[6:0] = High Z
D
X
6,10,11
PENH
IN
. See DC Characteristics for V
PEN
PENLK
= V
and V
PEN
PENH
Datasheet
4,5,6
and
CC