TE28F640J3C-150

Manufacturer Part NumberTE28F640J3C-150
DescriptionTE28F640J3C-150Intel StrataFlash Memory (J3)
ManufacturerIntel Corporation
TE28F640J3C-150 datasheet
 
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Page 35/72:

Device Commands

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9.2

Device Commands

voltage ≤ V
When the V
PEN
codes, or blocks are enabled. Placing V
and lock-bit configuration operations. Device operations are selected by writing specific
commands into the CUI.
commands.
Table 14. Command Bus-Cycle Definitions (Sheet 1 of 2)
Scalable or
Basic
Command
Command
(2)
Set
Read Array
SCS/BCS
Read Identifier Codes
SCS/BCS
Read Query
SCS
Read Status Register
SCS/BCS
Clear Status Register
SCS/BCS
Write to Buffer
SCS/BCS
Word/Byte Program
SCS/BCS
Block Erase
SCS/BCS
Block Erase, Program
SCS/BCS
Suspend
Block Erase, Program
SCS/BCS
Resume
Configuration
SCS
Set Block Lock-Bit
SCS
Datasheet
, only read operations from the Status Register, CFI, identifier
PENLK
on V
additionally enables block erase, program,
PENH
PEN
Table 14, “Command Bus-Cycle Definitions” on page 35
First Bus Cycle
Bus
Cycles
(3)
(4)
(5,6)
Req’d.
Oper
Addr
Data
1
Write
X
0xFF
≥ 2
Write
X
0X90
≥ 2
Write
X
0x98
2
Write
X
0x70
1
Write
X
0x50
> 2
Write
BA
0xE8
0x40 or
2
Write
X
0x10
2
Write
BA
0x20
1
Write
X
0xB0
1
Write
X
0xD0
2
Write
X
0xB8
2
Write
X
0x60
256-Mbit J3 (x8/x16)
defines these
Second Bus Cycle
Notes
(3)
(4)
(5,6)
Oper
Addr
Data
1
Read
IA
ID
1,7
Read
QA
QD
1
Read
X
SRD
1,8
1
1,9, 10,
Write
BA
N
11
Write
PA
PD
1,12,13
Write
BA
0xD0
1,11,12
1,12,14
1,12
Write
X
CC
1
Write
BA
0x01
1
35