CY7C0831V-167AC Cypress Semiconductor Corporation., CY7C0831V-167AC Datasheet

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CY7C0831V-167AC

Manufacturer Part Number
CY7C0831V-167AC
Description
CY7C0831V-167ACCypress Semiconductor [FLEx18-TM 3.3V 32K/64K/128K/256K/512K x 18 Synchronous Dual-Port RAM]
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

Specifications of CY7C0831V-167AC

Case
QFP-120L

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Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C0831V-167AC
Manufacturer:
CY
Quantity:
7
Cypress Semiconductor Corporation
Document #: 38-06059 Rev. *K
Features
• True dual-ported memory cells that allow simultaneous
• Synchronous pipelined operation
• Family of 512-Kbit, 1-Mbit, 2-Mbit, 4-Mbit and 9-Mbit
• Pipelined output mode allows fast operation
• 0.18-micron CMOS for optimum speed and power
• High-speed clock to data access
• 3.3V low power
• Mailbox function for message passing
• Global master reset
• Separate byte enables on both ports
• Commercial and industrial temperature ranges
• IEEE 1149.1-compatible JTAG boundary scan
• 144-ball FBGA (13 mm × 13 mm) (1.0 mm pitch)
• 120TQFP (14 mm x 14 mm x 1.4 mm)
• Counter wrap around control
• Counter readback on address lines
• Mask register readback on address lines
• Dual Chip Enables on both ports for easy depth
Table 1. Product Selection Guide
Density
Part Number
Max. Speed (MHz)
Max. Access Time - clock to Data (ns)
Typical operating current (mA)
Package
access of the same memory location
devices
expansion
— Active as low as 225 mA (typ)
— Standby as low as 55 mA (typ)
— Internal mask register controls counter wrap-around
— Counter-interrupt flags to indicate wrap-around
— Memory block retransmit operation
FLEx18
CY7C0837V
144 FBGA
(32K x 18)
3901 North First Street
512-Kbit
TM
PRELIMINARY
167
225
4.0
3.3V 32K/64K/128K/256K/512K x 18
CY7C0830V
(64K x 18)
120 TQFP
144 FBGA
Functional Description
The FLEx18 family includes 512-Kbit, 1-Mbit, 2-Mbit, 4-Mbit
and 9-Mbit pipelined, synchronous, true dual-port static RAMs
that are high-speed, low-power 3.3V CMOS. Two ports are
provided, permitting independent, simultaneous access to any
location in memory. The result of writing to the same location
by more than one port at the same time is undefined. Registers
on control, address, and data lines allow for minimal set-up
and hold time.
During a Read operation, data is registered for decreased
cycle time. Each port contains a burst counter on the input
address register. After externally loading the counter with the
initial address, the counter will increment the address inter-
nally (more details to follow). The internal Write pulse width is
independent of the duration of the R/W input signal. The
internal Write pulse is self-timed to allow the shortest possible
cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce the static power
consumption. One cycle with chip enables asserted is required
to reactivate the outputs.
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap-around, counter interrupt (CNTINT)
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST).
The CY7C0833V device in this family has limited features.
Please
Operations
1-Mbit
167
225
4.0
Synchronous Dual-Port RAM
see
[15]
CY7C0831V
(128K x 18)
on page 6 for details.
120 TQFP
144 FBGA
San Jose
Address
2-Mbit
167
225
4.0
CY7C0830V/CY7C0831V
CY7C0832V/CY7C0833V
,
CA 95134
Counter
CY7C0832V
(256K x 18)
144 FBGA
120 TQFP
4-Mbit
167
225
4.0
and
CY7C0837V
Mask
408-943-2600
CY7C0833V
July 06, 2004
(512K x 18)
144 FBGA
9-Mbit
133
270
4.7
Register

Related parts for CY7C0831V-167AC

CY7C0831V-167AC Summary of contents

Page 1

... FBGA 120 TQFP 120 TQFP 144 FBGA 144 FBGA • 3901 North First Street • San Jose CY7C0837V CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V Address Counter and Mask Register 2-Mbit 4-Mbit 9-Mbit (256K x 18) (512K x 18) CY7C0832V CY7C0833V 167 167 133 4 ...

Page 2

... CNTRST L Mirror Reg CLK L CNTINT L Interrupt INT L Logic Note: 1. CY7C0837V has 15 address CY7C0830V has 16 address bits, CY7C0831V has 17 address bits, CY7C0832V has 18 address bits and CY7C0833V has 19 address bits Document #: 38-06059 Rev. *K PRELIMINARY I/O I/O Control Control True Dual-Ported RAM Array Address Address ...

Page 3

... Leave this ball unconnected for CY7C0837V and CY7C0830V 4. Leave this ball unconnected for CY7C0837V, CY7C0830V and CY7C0831V 5. Leave this ball unconnected for CY7C0837V, CY7C0830V, CY7C0831V and CY7C0832V 6. These balls are not applicable for CY7C0833V device. They need to be tied to VDDIO. 7. These balls are not applicable for CY7C0833V device. They need to be tied to VSS. ...

Page 4

... 13L Notes: 9. Leave this pin unconnected for CY7C0830V 10. Leave this pin unconnected for CY7C0830V and CY7C0831V Document #: 38-06059 Rev. *K PRELIMINARY 120-pin Thin Quad Flat Pack (TQFP) Top View CY7C0830V / CY7C0831V / CY7C0832V CY7C0837V CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V ...

Page 5

... JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally TDO three-stated except when captured data is shifted out of the JTAG TAP. V Ground Inputs Power Inputs. DD Document #: 38-06059 Rev. *K CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V PRELIMINARY Description . MAX CY7C0837V is asserted LOW when L Page ...

Page 6

... At least one of BE0, BE1 must be LOW. 14. A18x for CY7C0832V, therefore the Interrupt Addresses are 3FFFF and 3FFFE. A18x and A17x are NC for CY7C0831V, therefore the Interrupt addresses are 1FFFF and 1FFFE; A18x, A17x and A16x are NC for CY7C0830V, therefore the Interrupt Addresses are FFFF and FFFE;A18x, A17x, A16x and A15x are NC for CY7C0837V, therefore the Interrupt Addresses are 7FFF and 7FFE ...

Page 7

... X X Mask Reset Reset mask register to all 1s Mask Load Load mask register with value presented on the address lines Mask Readback Read out mask register value on address lines Reserved Operation undefined CY7C0837V CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V [16, 17] Description Page ...

Page 8

... Mask Load Operation The mask register is loaded with the address value presented at the address lines. Not all values permit correct increment Document #: 38-06059 Rev. *K CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V PRELIMINARY operations. Permitted values are of the form 2 From the most significant bit to the least significant bit, permitted values have zero or more “ ...

Page 9

... Figure 1. Counter, Mask, and Mirror Logic Block Diagram Document #: 38-06059 Rev. *K PRELIMINARY Mask Register Counter/ Address Register Load/Increment Mirror Counter Increment Logic Wrap 17 Bit 0 +1 Wrap 1 Detect CY7C0837V CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V Address RAM Decode Array To Readback and Address Decode 17 Wrap To Counter [1] Page ...

Page 10

... The user can use these materials to easily integrate the devices into the board’s boundary scan environment. Further information can be found in the Cypress application note Using JTAG Boundary Scan For System in a Package (SIP) Dual-Port SRAMs. CY7C0837V CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V ...

Page 11

... Figure 3. Scan Chain for 9Mb Device Reserved for version number. Defines Cypress part number for CY7C0832V Defines Cypress part number for CY7C0831V Defines Cypress part number for CY7C0830V Defines Cypress part number for CY7C0837V. Allows unique identification of the DP family device vendor. ...

Page 12

... CY7C0833V 90 115 160 210 55 75 160 210 Description Test Conditions ° Input Capacitance MHz 3.3V DD Output Capacitance Input Capacitance Output Capacitance CY7C0837V CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V + 0.5V DD Ambient Temperature V DD 0°C to +70°C 3.3V±165 mV –40°C to +85°C 3.3V±165 mV -133 -100 Unit 2.4 2.4 0.4 0.4 2.0 2.0 0.8 0.8 – ...

Page 13

... CY7C0837V CY7C0837V CY7C0830V CY7C0830V CY7C0831V CY7C0831V CY7C0832V CY7C0832V Min. Max. Min. 167 6.0 7.5 2.7 3.0 2.7 3.0 2.0 2.0 2.3 2.5 0.6 0.6 2.3 2.5 0.6 0.6 2.3 2.5 0.6 0.6 2.3 2.5 0.6 0.6 2.3 2.5 0.6 0.6 2.3 2.5 0.6 0.6 2.3 2.5 0.6 0.6 2.3 2.5 CY7C0837V CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V 3. 590 Ω 435 Ω 90% 10% < -133 -100 CY7C0833V CY7C0833V Max. Min. Max. Min. Max. 133 133 100 7.5 10 3.0 4.0 3.0 4.0 2.0 2.0 3.0 2.0 2.0 3.0 2.5 3.0 0.6 0.6 2.5 3.0 0.6 0 2.5 3.0 0.6 0.6 2.5 3.0 0.6 0.6 NA ...

Page 14

... Master Reset Recovery Time RSR t Master Reset to Outputs Inactive RSF t Master Reset to Counter Interrupt RSCNTINT Flag Reset Time Document #: 38-06059 Rev. *K CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V PRELIMINARY (continued) -167 -133 CY7C0837V CY7C0837V CY7C0830V CY7C0830V CY7C0833V CY7C0831V CY7C0831V CY7C0832V CY7C0832V Min. Max. Min. Max. Min. 0.6 0.6 2.3 2.5 0.6 0.6 4.0 4 4.0 0 4.4 4 ...

Page 15

... Test Data-In TDI Test Data-Out TDO Document #: 38-06059 Rev. *K PRELIMINARY Description TMSS t TMSH t TDIS t TDIH t TDOX t TDOV CY7C0837V CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V CY7C0837V/CY7C0830V CY7C0831V/CY7C0832V Unit CY7C0833V Min. Max. 10 MHz 100 TCYC Page ...

Page 16

... Document #: 38-06059 Rev. *K PRELIMINARY t RSR ACTIVE t CYC2 t CL2 A A n+1 n+2 t CD2 CKLZ following the next rising edge of the clock. IH with CNT/MSK = V IL CY7C0837V CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V n n+1 t OHZ t OLZ t OE constantly loads the address on the rising edge of the CLK. IH Page n+2 ...

Page 17

... n+1 n CD2 CKHZ Q n READ NO OPERATION CY7C0837V CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V CD2 CKHZ CKHZ CKLZ CD2 CKHZ CD2 CKLZ CKLZ ...

Page 18

... PRELIMINARY [32, 35, 37, 38 n+1 n+2 n n+2 n+3 t CD2 OHZ READ WRITE [37] t SAD t SCN t CD2 n COUNTER HOLD READ WITH COUNTER CY7C0837V CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V A A n+4 n+5 t CD2 READ t HAD t HCN Q n+2 READ WITH COUNTER Page n+4 Q n+3 ...

Page 19

... ADDRESS n INTERNAL A n ADDRESS t t SAD HAD ADS CNTEN t t SCN HCN D DATA WRITE EXTERNAL ADDRESS Document #: 38-06059 Rev. *K PRELIMINARY [38 n+1 n+1 n+2 WRITE WITH WRITE COUNTER COUNTER HOLD CY7C0837V CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V n+2 n+3 n n+3 n+4 WRITE WITH COUNTER Page ...

Page 20

... MRST = CNT/MSK = HIGH 40. No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset. Document #: 38-06059 Rev. *K PRELIMINARY 0 t CD2 t CKLZ WRITE READ READ ADDRESS 0 ADDRESS 1 CY7C0837V CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V ...

Page 21

... the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines. Document #: 38-06059 Rev. *K PRELIMINARY [41, 42, 43, 44 CA2 CM2 n CD2 CKHZ CKLZ Q n INCREMENT in next clock cycle. CKLZ . CKHZ CY7C0837V CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V A A n+4 n+2 n n+1 n+2 n+3 Page ...

Page 22

... CKLZ n t CCS CD2 CNTRST = MRST = CNT/MSK = HIGH. 1 CY7C0837V CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V violated, indeterminate data will be Read out. CCS + t ) after the rising edge of R_Port's clock. CYC2 CD2 + t ) after the rising edge of R_Port's clock. CYC2 CD2 Page ...

Page 23

... CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value. 51. The mask register assumed to have the value of 3FFFFh. 52. Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value. Document #: 38-06059 Rev. *K CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V PRELIMINARY 3FFFE ...

Page 24

... Document #: 38-06059 Rev. *K PRELIMINARY n SINT 7FFFF m m+1 [1, 16, 58, 59, 60] Outputs CE R/W DQ – High High OUT H X High-Z CY7C0837V CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V A A n+2 n+3 t RINT A A m+3 m+4 Operation 17 Deselected Deselected Write Read Outputs Disabled Page ...

Page 25

... Speed Package (MHz) Ordering Code Name 167 CY7C0831V-167BBC BB144 167 CY7C0831V-167AC 133 CY7C0831V-167BBC BB144 CY7C0831V-167BBI BB144 133 CY7C0831V-167AC CY7C0831V-167AI 64K × 18 (1-Mbit) 3.3V Synchronous CY7C0830V Dual-Port SRAM Speed Package (MHz) Ordering Code Name 167 CY7C0830V-167BBC BB144 167 CY7C0830V-167AC 133 CY7C0830V-133BBC BB144 CY7C0830V-133BBI ...

Page 26

... 13.00±0.10 SEATING PLANE C Document #: 38-06059 Rev. *K PRELIMINARY 144 FBGA ( 1.6 MM) BB144 BOTTOM VIEW A B 0.15(4X) CY7C0837V CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V Ø0. Ø0. +0.10 Ø0.50 (144X) -0. ...

Page 27

... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V ...

Page 28

... Updated selection guide table and moved to the front page. Updated block diagram to reflect x18 configuration. Added preliminary status back due to the addition of the new devices. RYQ Minor Change: Correct the revision indicated on the footer. CY7C0837V CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V SB3 SB3 , t for the CY7C0853V to 4.7 ns ...

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