CY7C4251-25AI Cypress Semiconductor Corporation., CY7C4251-25AI Datasheet
CY7C4251-25AI
Related parts for CY7C4251-25AI
CY7C4251-25AI Summary of contents
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... Synchronous FIFOs Features • High-speed, low-power, First-In, First-Out (FIFO) memories — 64 × 9 (CY7C4421) — 256 × 9 (CY7C4201) — 512 × 9 (CY7C4211) — 1K × 9 (CY7C4221) — 2K × 9 (CY7C4231) — 4K × 9 (CY7C4241) — 8K × 9 (CY7C4251) • High-speed 100-MHz operation (10 ns Read/Write cycle time) • ...
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... When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected HIGH, the FIFO’s outputs are in High-Z (high-impedance) state. CY7C4421/4201/4211/4221 CY7C4231/4241/4251 -15 -25 66 CY7C4231 CY7C4241 CY7C4251 2K × × 9 Description Page Unit MHz ICC1 8K × 9 ...
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Functional Description The CY7C42X1 provides four status pins: Empty, Full, Almost Empty, Almost Full. The Almost Empty/Almost Full flags are programmable to single word granularity. The programmable flags default to Empty – 7 and Full – 7. The flags are ...
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Empty Offset (LSB) Reg. Default Value = 007h Full Offset (LSB) Reg Default Value = 007h × Empty Offset (LSB) Reg. ...
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... Empty Offset ( default value Full Offset ( default value). Document #: 38-06016 Rev. *C (256 – m), CY7C4211 (512 – m), CY7C4221 (1K – m), CY7C4231 (2K – m), CY7C4241 (4K – m), and CY7C4251 (8K – m). PAF is set HIGH by the LOW-to-HIGH transition of WCLK when the number of available memory locations is greater than m. ...
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Width Expansion Configuration Word width may be increased simply by connecting the corre- sponding input controls signals of multiple devices. A composite flag should be created for each of the end-point status flags (EF and FF). The partial status flags ...
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Maximum Ratings [4] (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ...................................–65 Ambient Temperature with Power Applied...............................................–55 Supply Voltage to Ground Potential ............... –0.5V to +7.0V DC Voltage Applied to Outputs in ...
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AC Test Loads and Waveforms R1 1.1 K Ω 5V OUTPUT C L INCLUDING JIG AND SCOPE Switching Characteristics Over the Operating Range Parameter Description t Clock Cycle Frequency S t Data Access Time A t Clock Cycle Time CLK ...
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Switching Waveforms Write Cycle Timing WCLK D – WEN1 WEN2 (if applicable SKEW1 RCLK REN1,REN2 Read Cycle Timing RCLK t ENS REN1,REN2 EF Q – OLZ OE WCLK WEN1 WEN2 Notes: 15. t ...
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Switching Waveforms (continued) [17] Reset Timing RS REN1, REN2 WEN1 [18] WEN2/LD EF,PAE FF,PAF First Data Word Latency after Reset with Simultaneous Read and Write WCLK – (FIRST 0 8 ...
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Switching Waveforms (continued) Empty Flag Timing WCLK t DS DATAWRITE1 D – ENH ENS WEN1 WEN2 (if applicable ENS ENH t RCLK t SKEW1 EF REN1, REN2 LOW OE DATA IN OUTPUT REGISTER Q ...
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Switching Waveforms (continued) Full Flag Timing NO Write WCLK [15] t SKEW1 D – WEN1 WEN2 (if applicable) RCLK t ENS REN1, REN2 LOW OE Q –Q DATA IN OUTPUT REGISTER 0 8 Programmable Almost Empty Flag ...
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... PAF offset = m. 27. 64-m words for CY7C4421, 256 – m words in FIFO for CY7C4201, 512 – m words for CY7C4211, 1024 – m words for CY7C4221, 2048 – m words for CY7C4231, 4096 – m words for CY7C4241, 8192 – m words for CY7C4251. 28 the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge ...
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Switching Waveforms (continued) Read Programmable Registers t CLK t CLKH RCLK t ENS WEN2/LD t ENS REN1, REN2 Q – Document #: 38-06016 Rev. *C CY7C4421/4201/4211/4221 t CLKL t ENH t A UNKNOWN PAE OFFSET LSB CY7C4231/4241/4251 PAF ...
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Typical AC and DC Characteristics NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 1 25°C 0 100 MHz 0.6 4 4.5 5 5.5 SUPPLY VOLTAGE (V) NORMALIZED t vs. SUPPLY A ...
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Ordering Information Synchronous FIFO Speed (ns) Ordering Code 10 CY7C4421-10AC CY7C4421-10JC CY7C4421-10JXC 15 CY7C4421-15AC CY7C4421-15JC 256 x 9 Synchronous FIFO Speed (ns) Ordering Code 10 CY7C4201-10AC CY7C4201-10JC 15 CY7C4201-15AC CY7C4201-15AXC CY7C4201-15JC CY7C4201-15JXC 25 CY7C4201-25AC CY7C4201-25JC CY7C4201-25AI 512 ...
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... CY7C4251-10AC CY7C4251-10JC CY7C4251-10JXC CY7C4251-10AI CY7C4251-10AXI 15 CY7C4251-15AC CY7C4251-15AXC CY7C4251-15JC CY7C4251-15JXC 25 CY7C4251-25AC CY7C4251-25JC CY7C4251-25AI Document #: 38-06016 Rev. *C CY7C4421/4201/4211/4221 Package Package Name Type A32 32-lead Thin Quad Flatpack J65 32-lead Plastic Leaded Chip Carrier A32 32-lead Thin Quad Flatpack A32 32-lead Pb-Free Thin Quad Flatpack ...
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Package Diagrams 32-lead Thin Plastic Quad Flatpack 7 × 7 × 1.0 mm A32 32-lead Pb-Free Thin Plastic Quad Flatpack 7 × 7 × 1.0 mm A32 32-Lead Pb-Free Plastic Leaded Chip Carrier J65 All product and company names mentioned ...
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... Power up requirements added to Maximum Ratings Information ESH Added Pb-Free logo to top of front page Added CY7C4421-10JXC, CY7C4201-15AXC. CY7C4201-15JXC, CY7C4211-10AXI, CY7C4211-15AXC, CY7C4211-15JXC, CY7C4221-15AXC, CY7C4221-15JXC, CY7C4231-15JXC, CY7C4231-15AXC, CY7C4241-10AXC, CY7C4241-15AXC, CY7C4241-15JXC, CY7C4251-10JXC, CY7C4251-10AXI, CY7C4251-15AXC, CY7C4251-15JXC CY7C4421/4201/4211/4221 CY7C4231/4241/4251 Description of Change unit from mA to µA (typo) IX Page ...
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