MACH210-18JI Advanced Micro Devices, MACH210-18JI Datasheet

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MACH210-18JI

Manufacturer Part Number
MACH210-18JI
Description
High-density EE CMOS programmable logic, 18ns
Manufacturer
Advanced Micro Devices
Datasheet

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MACH210A-7/10/12
MACH210-12/15/20
MACH210AQ-12/15/20
High-Density EE CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
GENERAL DESCRIPTION
The MACH210 is a member of AMD’s high-performance
EE CMOS MACH 2 device family. This device has
approximately six times the logic macrocell capability of
the popular PAL22V10 without loss of speed.
The MACH210 consists of four PAL blocks intercon-
nected by a programmable switch matrix. The four PAL
blocks are essentially “PAL22V16” structures complete
with product-term arrays and programmable macro-
cells, including additional buried macrocells. The switch
matrix connects the PAL blocks to each other and to all
input pins, providing a high degree of connectivity
between the fully-connected PAL blocks. This allows
designs to be placed and routed efficiently.
The MACH210 has two kinds of macrocell: output and
buried. The MACH210 output macrocell provides regis-
44 Pins
64 Macrocells
7.5 ns t
12 ns t
133 MHz f
38 Inputs; 210A Inputs have built-in pull-up
resistors
PD
PD
FINAL
Industrial
CNT
Commercial
COM’L: -7/10/12/15/20, Q-12/15/20
tered, latched, or combinatorial outputs with program-
mable polarity. If a registered configuration is chosen,
the register can be configured as D-type or T-type to
help reduce the number of product terms. The register
type decision can be made by the designer or by the
software. All output macrocells can be connected to an
I/O cell. If a buried macrocell is desired, the internal
feedback path from the macrocell can be used, which
frees up the I/O pin for use as an input.
The MACH210 has dedicated buried macrocells which,
in addition to the capabilities of the output macrocell,
also provide input registers or latches for use in
synchronizing signals and reducing setup time require-
ments.
Peripheral Component Interconnect (PCI)
compliant
32 Outputs
64 Flip-flops; 2 clock choices
4 “PAL22V16” blocks with buried macrocells
Pin-compatible with MACH110, MACH111,
MACH211, and MACH215
IND: -12/14/18/24
Publication# 14128
Issue Date: May 1995
Rev. I
Advanced
Devices
Amendment /0
Micro

Related parts for MACH210-18JI

MACH210-18JI Summary of contents

Page 1

... PAL blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected PAL blocks. This allows designs to be placed and routed efficiently. The MACH210 has two kinds of macrocell: output and buried. The MACH210 output macrocell provides regis- COM’L: -7/10/12/15/20, Q-12/15/20 Peripheral Component Interconnect (PCI) ...

Page 2

... I/O Cells Macrocells Macrocells AND Logic Array and Logic Allocator 22 Switch Matrix AND Logic Array and Logic Allocator OE Macrocells Macrocells I/O Cells 8 I/O –I MACH210-7/10/12/15/20, Q-12/15/20 I – – CLK / CLK / 14128I-1 ...

Page 3

... Pin-compatible with MACH110, MACH111, MACH211, and MACH215. PLCC MACH210-7/10/12/15/20, Q-12/15/20 AMD I CLK GND 14128I-2 3 ...

Page 4

... Pin-compatible with MACH111 and MACH211. PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output V = Supply Voltage CC 4 TQFP MACH210-7/10/12/15/20, Q-12/15/20 I/O27 I/O26 I/O25 I/O24 CLK1/I5 GND I4 I3 I/O23 I/O22 I/O21 14128I-3 ...

Page 5

... MACH210A-10 VC MACH210A-12 MACH210-12 MACH210-15 MACH210-20 JC MACH210AQ-12 MACH210AQ-15 MACH210AQ-20 MACH210-7/10/12/15/20, Q-12/15/20 (Com’l) MACH 210A - Valid Combinations The Valid Combinations table lists configurations planned to be supported in volume for this device. Con- sult the local AMD sales office to confirm availability of specific valid combinations or to check on newly re- leased combinations ...

Page 6

... The Valid Combinations table lists configurations planned to be supported in volume for this device. Con- sult the local AMD sales office to confirm availability of specific valid combinations or to check on newly re- leased combinations. MACH210-12/14/18/24 (Ind) OPTIONAL PROCESSING Blank = Standard Processing OPERATING CONDITIONS I = Industrial (– +85 C) ...

Page 7

... The Logic Allocator The logic allocator in the MACH210 takes the 64 logic product terms and allocates them to the 16 macrocells as needed. Each macrocell can be driven product terms. The design software automatically configures the logic allocator when fitting the design into the device ...

Page 8

... AMD The I/O Cell The I/O cell in the MACH210 consists of a three-state output buffer. The three-state buffer can be configured in one of three ways: always enabled, always disabled, or controlled by a product term. If product term control is chosen, one of two product terms may be used to provide the control. The two product terms that are available are common to all I/O cells in a PAL block ...

Page 9

... Switch Matrix Figure 1. MACH210 PAL Block MACH210-7/10/12/15/20, Q-12/15/20 AMD Output Enable Output Enable Asynchronous Reset Asynchronous Preset I/O Cell Output M Macro 0 cell 2 Buried Macro M cell 1 2 I/O Cell Output M Macro 2 cell ...

Page 10

... 0 Max (Note 3) OUT Outputs Open ( 5 MHz (Note 4) and I (or I and OZL IH OZH MACH210A-7 (Com’l) ) Operating + with +4. +5.25 V Min Typ Max 2.4 0.5 2.0 0.8 10 –100 10 –100 –30 –160 = 0 mA) ...

Page 11

... Transparent Input Latch to Output Latch Gate Test Conditions MHz OUT D-Type T-Type LOW HIGH D-Type T-Type D-Type ) CNT T-Type D-Type T-Type LOW HIGH MACH210A-7 (Com’l) AMD Typ Unit = Min Max Unit 7.5 ns 5 ...

Page 12

... APR t Input, I/O, or Feedback to Output Enable EA t Input, I/O, or Feedback to Output Disable ER Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 12 MACH210A-7 (Com’l) -7 Min Max Unit 11 ...

Page 13

... (Note 0 Max (Note 3) OUT 5V MHz CC A (Note 4) and I (or I and OZL IH OZH MACH210A-10/12 (Com’l) AMD ) Operating + with +4. +5.25 V Min Typ Max Unit 2.4 V 0.5 V 2 –100 A ...

Page 14

... MHz OUT D-Type T-Type LOW HIGH D-Type 1/( T-Type D-Type ) CNT T-Type 1/( D-Type T-Type LOW HIGH 1/( WICL WICH MACH210A-10/12 (Com’l) Typ Unit = -10 -12 Min Max Min Max Unit 6 7 ...

Page 15

... Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. 3. Parameters measured with 16 outputs switching. MACH210A-10/12 (Com’l) AMD -10 -12 Min Max ...

Page 16

... (Note 0 Max (Note 3) OUT 5V MHz CC A (Note 4) and I (or I and OZL IH OZH MACH210A-12/14 (Ind) ) Operating – + with +4 +5.5 V Min Typ Max 2.4 0.5 2.0 0.8 10 –100 10 –100 –30 –160 135 Unit ...

Page 17

... MHz OUT D-Type T-Type LOW HIGH D-Type 1/( T-Type D-Type ) CNT T-Type 1/( D-Type T-Type LOW HIGH 1/( WICL WICH MACH210A-12/14 (Ind) AMD Typ Unit = -12 -14 Min Max Min Max Unit 7.5 ...

Page 18

... Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. 3. Parameters measured with 16 outputs switching. 18 MACH210A-12/14 (Ind) -12 -14 Min Max Min Max ...

Page 19

... (Note 0 Max (Note 3) OUT 5V MHz CC A (Note 4) and I (or I and OZL IH OZH MACH210-12/15/20 (Com’l) AMD ) Operating + with +4. +5.25 V Min Typ Max Unit 2.4 V 0.5 V 2 –10 A ...

Page 20

... T-type 62.5 D-type 83.3 ) CNT T-type 76.9 1/( 83 D-type 12 T-type 13 LOW 6 HIGH 6 1/( 83.3 WICL WICH MACH210-12/15/20 (Com’l) Typ Unit = -15 -20 Min Max Min Max Unit ...

Page 21

... These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. 3. Parameters measured with 16 outputs switching. -12 Min Max MACH210-12/15/20 (Com’l) AMD -15 -20 Min Max Min Max Unit ...

Page 22

... VIN = 5.25 V, VCC = Max (Note 2) VIN = 0 V, VCC = Max (Note 2) VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Note 3) VCC = MHz (Note 4) MACH210-14/18/24 (Ind – + ...

Page 23

... D-type 53 1/(tS + tCO) T-type 50 D-type 61.5 T-type 57 1/(tWL + tWH) 66.5 8 7 14.5 D-type 16 T-type LOW 7.5 HIGH 7.5 1/(tWICL + tWICH ) 66.5 2 7.5 19.5 MACH210-14/18/24 (Ind) AMD Typ Unit -18 -24 Min Max Min Max Unit 13 14 MHz 38 30 ...

Page 24

... These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. 3. Parameters measured with 16 outputs switching. 24 -14 Min Max 19.5 14.5 10 19.5 14.5 10 14.5 14.5 MACH210-14/18/24 (Ind) -18 -24 Min Max Min Max Unit ...

Page 25

... (Note 0 Max (Note 3) OUT MHz CC A (Note 4) and I (or I and OZL IH OZH MACH210AQ-12 (Com’l) AMD ) Operating + with +4. +5.25 V Min Typ Max Unit 2.4 V 0.5 V 2 –100 A ...

Page 26

... Test Conditions MHz OUT D-type T-type LOW HIGH D-type T-type D-type ) CNT T-type D-type T-type LOW HIGH MACH210AQ-12 (Com’l) Typ Unit = -12 Min Max Unit ...

Page 27

... Input, I/O, or Feedback to Output Disable ER Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. MACH210AQ-12 (Com’l) AMD -12 Min Max Unit 6 ns ...

Page 28

... (Note 0 Max (Note 3) OUT 5V MHz CC A (Note 4) and I (or I and OZL IH OZH MACH210AQ-15/20 (Com’l) ) Operating + with +4. +5.25 V Min Typ Max 2.4 0.5 2.0 0.8 10 –100 10 –100 –30 –160 45 Unit ...

Page 29

... D-type T-type LOW HIGH D-type 1/( T-type D-type ) CNT T-type D-type 1/( T-type D-type T-type LOW HIGH 1/( WICL WICH MACH210AQ-15/20 (Com’l) AMD Typ Unit = -15 -20 Min Max Min Max Unit ...

Page 30

... Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. 3. Parameters measured with 16 outputs switching. 30 MACH210AQ-15/20 (Com’l) -15 -20 Min Max Min ...

Page 31

... VIN = 5.25 V, VCC = Max (Note 2) VIN = 0 V, VCC = Max (Note 2) VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Note 3) VCC = MHz (Note 4) MACH210AQ-18/24 (Ind) AMD ) – + ...

Page 32

... Test Conditions VIN = 2.0 V VCC = 5 VOUT = 2 MHz D-type T-type LOW HIGH D-type 1/(tS + tCO) T-type D-type T-type D-type 1/(tS + tH) T-type D-type T-type LOW HIGH 1/(tWICL + tWICH ) MACH210AQ-18/24 (Ind) Typ Unit -18 -24 Min Max Min Max Unit 20 ...

Page 33

... Input, I/O, or Feedback to Output Disable (Note 3) Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. 3. Parameters measured with 16 outputs switching. MACH210AQ-18/24 (Ind) AMD -18 -24 Min Max ...

Page 34

... Output, LOW I (mA –3 –2 –1 –25 –50 –75 –100 –125 –150 Output, HIGH I (mA –2 – –20 –40 –60 –80 –100 Input MACH210-7/10/12/15/20, Q-12/15/ 1.0 14128I (V) OH 14128I 14128I-7 ...

Page 35

... The selected “typical” pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. Maximum frequency shown uses internal feedback and a D-type register. MACH210AQ Frequency (MHz) MACH210-7/10/12/15/20, Q-12/15/20 AMD MACH210A MACH210 80 90 100 14128I-8 35 ...

Page 36

... Furthermore, jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment. 36 200 lfpm air 400 lfpm air 600 lfpm air 800 lfpm air MACH210-7/10/12/15/20, Q-12/15/20 Typ TQFP PLCC Unit 11.3 15 ...

Page 37

... WL 14128I- Registered Input t HIR Input V T Register Clock t ICO V T Output Register Clock 14128I-14 Input Register to Output Register Setup MACH210-7/10/12/15/20, Q-12/15/20 AMD V T 14128I PDL 14128I-11 Latched Output (MACH 2, 3, and GWS 14128I-13 Gate Width (MACH 2, 3, and 4) ...

Page 38

... T 2. Input pulse amplitude 3 Input rise and fall times 2 ns–4 ns typical SIL HIL 14128I-16 Latched Input (MACH 2 and 4) t PDLL Latched Input and Output (MACH 2, 3, and 4) MACH210-7/10/12/15/20, Q-12/15/20 IGO SLL V T 14128I-17 ...

Page 39

... WICL 14128I-18 Input, I/ Feedback Registered V T Output t ARR Clock V T 14128I- 0. 0.5V OL Output Disable/Enable MACH210-7/10/12/15/20, Q-12/15/20 AMD WIGL 14128I-19 Input Latch Gate Width (MACH 2 and 4) t APW APR V 14128I-21 Asynchronous Preset 14128I-22 ...

Page 40

... State Permitted Unknown Does Not Center Apply Line is High- Impedance “Off” State Output Commercial 300 390 5 pF MACH210-7/10/12/15/20, Q-12/15/20 KS000010-PAL Test Point 14128I-23 Measured Output Value 2 1 – ...

Page 41

... All frequencies except f MAX other measured AC parameters. f ured directly. (SECOND CHIP SIR + MACH210-7/10/12/15/20, Q-12/15/20 AMD + t ). However type is the mini- MAX + t ). Usually, this minimum WH WL MAX no feedback.” . Because this involves no MAXIR no feed- MAX + the sum of ...

Page 42

... Min Pattern Data Retention Time Max Reprogramming Cycles 42 bipolar parts result, the device can be erased and reprogrammed, a feature which allows 100% testing at the factory. Min 10 20 100 MACH210-7/10/12/15/20, Q-12/15/20 Units Test Conditions Years Max Storage Temperature Years Max Operating Temperature Cycles Normal Programming Conditions ...

Page 43

... INPUT/OUTPUT EQUIVALENT SCHEMATICS ESD Protection 1 k Input 100 k Preload Feedback Circuitry Input I/O MACH210-7/10/12/15/20, Q-12/15/20 AMD V CC 100 14128I-25 43 ...

Page 44

... Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met Power-Up Reset Waveform MACH210-7/10/12/15/20, Q-12/15/20 can rise to its steady state, two CC Max Unit 10 s See Switching Characteristics V ...

Page 45

... All MACH 2 devices support both preload and observability. Contact individual programming vendors in order to verify programmer support. On Preload Off Mode Figure 2. Preload/Reset Conflict Set Reset Figure 3. Combinatorial Latch MACH210-7/10/12/15/20, Q-12/15/20 AMD Preloaded HIGH Preloaded HIGH 14128I-27 14128I-28 ...

Page 46

... PROsynthesis/AMD Software ComposerPIC (Requires MACH Fitter) Verilog, LeapFrog, RapidSim Simulators (Models also available from Logic Modeling) MacABEL (Requires SmartPart MACH Fitter) SmartCAT Circuit Analyzer ABEL (Requires MACH Fitter) (Requires MACH Fitter) SmartModel MACH210-7/10/12/15/20, Q-12/15/20 Ver. 2.0 Software Software TM Designer Ver. 3.3 TM Software TM -5 Software Synario ...

Page 47

... Schematic Design Tool 386+ Digital Simulation Tools MultiSIM Interactive Simulator ViewPLD or PROPLD (Requires PROSim Simulator MACH Fitter) ViewSim Simulator (Models for ViewSim also available from Logic Modeling) TEST GENERATION SYSTEM TM ATGEN MACH210-7/10/12/15/20, Q-12/15/20 AMD TM PLDSynthesis TM -XL Software TM SUSIE Simulator LASAR Test Generation Software ...

Page 48

... Hidden Creek Way, Suite H Cerritos, California 70703 (310) 926-6727 Advanced Micro Devices P.O. Box 3453, MS-1028 Sunnyvale, CA 94088-3453 (800) 222-9323 48 (subject to change) PROGRAMMER CONFIGURATION Pilot U84 BP1200 TM UniSite Model 3900 ALLPRO Sprint/Expert Stag Quazar Turpro-1 PROGRAMMER CONFIGURATION JTAG PROG MACHpro MACH210-7/10/12/15/20, Q-12/15/20 AutoSite TM –88 ...

Page 49

... Santa Clara, CA 95051 (408) 982-0660 Logical Systems Corp. P.O. Box 6184 Syracuse, NY 13217-6184 (315) 478-0722 Procon Technologies, Inc. 1333 Lawrence Expwy, Suite 207 Santa Clara, CA 95051 (408) 246-4456 (subject to change) PART NUMBER Contact Manufacturer Contact Manufacturer Contact Manufacturer Contact Manufacturer MACH210-7/10/12/15/20, Q-12/15/20 AMD 49 ...

Page 50

... Plastic Leaded Chip Carrier (measured in inches) .685 .695 .650 .656 Pin 1 I.D. .685 .695 .650 .656 .026 .050 REF .032 TOP VIEW 50 .062 .083 .042 .056 .009 .015 .090 .120 .165 .180 SIDE VIEW MACH210-7/10/12/15/20, Q-12/15/20 .500 .590 REF .630 .013 .021 SEATING PLANE 16-038-SQ PL 044 DA78 6-28-94 ae ...

Page 51

... Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, MACH, and PAL are registered trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 9.80 10.20 9.80 10.20 11.80 12.20 11 – 13 1.20 MAX 11 – 13 0.80 BSC MACH210-7/10/12/15/20, Q-12/15/20 AMD 11.80 12.20 16-038-PQT-2_AH PQT 44 5-4- ...

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