MACH211SP-10VC Advanced Micro Devices, MACH211SP-10VC Datasheet

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MACH211SP-10VC

Manufacturer Part Number
MACH211SP-10VC
Description
High-density EE CMOS programmable logic, 64 macrocells, 32 outputs, 64 flip-flops, 10ns
Manufacturer
Advanced Micro Devices
Datasheet
MACH211SP-7/10/12/15/20
High-Density EE CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
IN-SYSTEM PROGRAMMING
In-system programming allows the MACH211SP to be
programmed while soldered onto a system board. Pro-
gramming the MACH211SP in-system yields numer-
ous benefits at all stages of development: prototyping,
manufacturing, and in the field. Since insertion into a
programmer isn’t needed, multiple handling steps and
the resulting bent leads are eliminated. The design can
be modified in-system for design changes and debug-
ging while prototyping, programming boards in produc-
tion, and field upgrades.
GENERAL DESCRIPTION
The MACH211SP is a member of AMD’s EE CMOS
Performance Plus MACH 2 device family. This device
has approximately six times the logic macrocell capa-
bility of the popular PAL22V10 without loss of speed.
The MACH211SP consists of four PAL
connected by a programmable switch matrix. The four
PAL blocks are essentially “PAL26V16” structures com-
plete with product-term arrays and programmable
macrocells, which can be programmed as high speed
or low power, and buried macrocells. The switch matrix
connects the PAL blocks to each other and to all input
pins, providing a high degree of connectivity between
the fully-connected PAL blocks. This allows designs to
be placed and routed efficiently.
The MACH211SP has two kinds of macrocell: output
and buried. The MACH211SP output macrocell pro-
vides registered, latched, or combinatorial outputs with
JTAG-Compatible, 5-V in-system programming
44 Pins
64 Macrocells
7.5 ns t
10 ns t
133 MHz f
34 Bus-Friendly™ Inputs and I/Os
PD
PD
FINAL
Industrial
CNT
Commercial
COM’L: -7.5/10/12/15/20
blocks inter-
The MACH211SP offers advantages not available in
other CPLD architectures with in-system programming.
MACH devices have extensive routing resources for
pin-out retention; design changes resulting in pin-out
changes for other CPLDs cancel the advantages of
in-system programming. The MACH211SP can be em-
ployed in any JTAG (IEEE 1149.1) compliant chain.
programmable polarity. If a registered configuration is
chosen, the register can be configured as D-type or
T-type to help reduce the number of product terms. The
register type decision can be made by the designer or
by the software. All output macrocells can be con-
nected to an I/O cell. If a buried macrocell is desired,
the internal feedback path from the macrocell can be
used, which frees up the I/O pin for use as an input.
The MACH211SP has dedicated buried macrocells
which, in addition to the capabilities of the output
macrocell, also provide input registers or latches for
use in synchronizing signals and reducing setup time
requirements.
The MACH211SP is an enhanced version of the
MACH211, adding the JTAG-compatible in-system pro-
gramming feature.
Peripheral Component Interconnect (PCI)
compliant (-7/-10)
Programmable power-down mode
32 Outputs
64 Flip-flops; 2 clock choices
4 “PAL26V16” blocks with buried macrocells
Improved routing over the MACH210
IND: -10/12/14/18/24
Publication# 20405
Issue Date: February 1996
Rev: B Amendment/0

Related parts for MACH211SP-10VC

MACH211SP-10VC Summary of contents

Page 1

... GENERAL DESCRIPTION The MACH211SP is a member of AMD’s EE CMOS Performance Plus MACH 2 device family. This device has approximately six times the logic macrocell capa- bility of the popular PAL22V10 without loss of speed. ...

Page 2

... I/O Cells 8 I/O –I I/O –I I/O Cells Macrocells Macrocells AND Logic Array and Logic Allocator 26 Switch Matrix AND Logic Array and Logic Allocator OE Macrocells Macrocells I/O Cells 8 I/O –I MACH211SP-7/10/12/15/ CLK / CLK / 20405B-1 ...

Page 3

... CONNECTION DIAGRAM MACH211SP Top View I/O5 I/O6 I/O7 TDI CLK0/I0 GND TCK I/O8 I/O9 I/O10 I/O11 PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output V = Supply Voltage CC 44-Pin PLCC TDI ...

Page 4

... CONNECTION DIAGRAM MACH211SP Top View I/O5 I/O6 I/O7 TDI CLK0/I0 GND TCK I/O8 I/O9 I/O10 I/O11 PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output V = Supply Voltage CC 4 44-Pin TQFP TDI = Test Data In TCK = Test Clock ...

Page 5

... The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combina- tions and to check on newly released combinations. MACH211SP-7/10/12/15/20 (Com’l) OPTIONAL PROCESSING Blank = Standard Processing OPERATING CONDITIONS ...

Page 6

... The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combina- tions and to check on newly released combinations. JI MACH211SP-10/12/14/18/24 (Ind) I OPTIONAL PROCESSING Blank = Standard Processing OPERATING CONDITIONS I = Industrial (– ...

Page 7

... I/O cell in the PAL block. All flip-flops within the PAL block are initialized together. The Switch Matrix The MACH211SP switch matrix is fed by the inputs and feedback signals from the PAL blocks. Each PAL block provides 16 internal feedback signals and 8 I/O feed- back signals. The switch matrix distributes these sig- nals back to the PAL blocks in an effi ...

Page 8

... Test Mode Select (TMS), Test Clock (TCK), Test Data In (TDI), and Test Data Out (TDO). The MACH211SP can be employed in any JTAG (IEEE 1149.1) compli- ant chain. While the MACH211SP is fully JTAG com- patible, it supports the BYPASS instruction, not the EXTEST and SAMPLE/PRELOAD instructions. The MACH211SP can be programmed across the commer- cial temperature range ...

Page 9

... Switch Matrix Figure 1. MACH211SP PAL Block MACH211SP-7/10/12/15/20 Output Enable Output Enable Asynchronous Reset Asynchronous Preset I/O Cell Output Macro M Cell 0 Buried Macro M Cell 1 I/O Cell Output M Macro 2 Cell Buried Macro M Cell ...

Page 10

... 0 Max (Notes 3, 5) OUT MHz (Note MHz (Note and I (or I and OZL IH OZH MACH211SP-7/10 (Com’ Min Typ Max = 2 0 2.0 0.8 10 –10 10 –10 –30 – ...

Page 11

... S CO T-type 91 D-type 133 ) CNT T-type 125 1/( 166 5 D-type 9 T-type 10 LOW 3 HIGH 3 166 7.5 MACH211SP-7/10 (Com’l) Typ Unit -10 Max Min Max Unit 7 6 MHz 74 MHz 100 MHz ...

Page 12

... These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 2. See Switching Test Circuit for test conditions signal is powered-down, this parameter must be added to its respective high-speed parameter. 12 Min MACH211SP-7/10 (Com’l) -7 -10 Max Min Max Unit 12.5 ...

Page 13

... 0 Max (Notes 3, 5) OUT MHz (Note MHz (Note and I (or I and OZL IH OZH MACH211SP-12/15/20 (Com’ Min Typ Max = 2 0 2.0 0.8 10 –10 10 –10 –30 – ...

Page 14

... D-type 83.3 ) CNT T-type 76.9 1/( 83 D-type 12 T-type 13 LOW 6 HIGH 6 1/( 83.3 WICL WICH 2 2 MACH211SP-12/15/20 (Com’l) Typ Unit -15 -20 Min Max Min Max Unit ...

Page 15

... See Switching Test Circuit for test conditions signal is powered-down, this parameter must be added to its respective high-speed parameter. -12 Min Max MACH211SP-12/15/20 (Com’l) -15 -20 Min Max Min Max Unit ...

Page 16

... 0 Max (Notes 3, 5) OUT MHz (Note MHz (Note and I (or I and OZL IH OZH MACH211SP-10/12 (Ind Min Typ Max = 2 0 2.0 0.8 10 –10 10 –10 –30 –160 ...

Page 17

... T-type 74 D-type 100 ) CNT T-type 91 1/( 100 D-type 10 T-type 11 LOW 5 HIGH 5 1/( 100 WICL WICH 2 2 MACH211SP-10/12 (Ind) Typ Unit -10 -12 Max Min Max Unit 7 MHz 59 MHz ...

Page 18

... These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit for test conditions signal is powered-down, this parameter must be added to its respective high-speed parameter. 18 Min 8 MACH211SP-10/12 (Ind) -10 -12 Max Min Max Unit 10 ...

Page 19

... 0 Max (Notes 3, 5) OUT MHz (Note MHz (Note and I (or I and OZL IH OZH MACH211SP-14/18/24 (Ind Min Typ Max = 2 0 2.0 0.8 10 –10 10 –10 –30 –160 ...

Page 20

... S CO T-type 50 D-type 61.5 ) CNT T-type 57 1 7 D-type 14.5 T-type 16 LOW 7.5 HIGH 7.5 1/( 66.5 WICL WICH 2.5 3 20.5 MACH211SP-14/18/24 (Ind) Typ Unit -18 -24 Min Max Min Max Unit 13 14 MHz 38 30.5 MHz 53 38 ...

Page 21

... See Switching Test Circuit for test conditions signal is powered-down, this parameter must be added to its respective high-speed parameter. -14 Min Max Min 23 11 14.5 16 19.5 7.5 7.5 19.5 19.5 14 19.5 14 14.5 14 MACH211SP-14/18/24 (Ind) -18 -24 Max Min Max Unit 26 ...

Page 22

... The selected “typical” pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. Maximum frequency shown uses internal feedback and a D-type register Frequency (MHz) MACH211SP-7/10/12/15/20 High Speed Low Power 20405B-5 ...

Page 23

... Therefore, the measurements can only be used in a similar environment. TQFP thermal measurements are taken with components on a six-layer printed circuit board. TQFP 11.3 200 lfpm air 400 lfpm air 33.7 600 lfpm air 32.6 800 lfpm air measurement relative to a specific location on the jc MACH211SP-7/10/12/15/20 Typ PLCC Unit 4 C/W 41 30.4 C/W 35 18.5 C/W 15 ...

Page 24

... Out 20405B-7 Gate t WL 20405B-9 Registered V T Input t HIR Input V Register T Clock t ICO Output V T Register Clock 20405B-11 Input Register to Output Register Setup MACH211SP-7/10/12/15/ 20405B PDL 20405B-8 Latched Output GWL 20405B-10 Gate Width ...

Page 25

... Latch Gate Notes 1 Input pulse amplitude 3 Input rise and fall times 2 ns–4 ns typical SIL HIL Latched Input t IGOL t IGS Latched Input and Output MACH211SP-7/10/12/15/ IGO V T 20405B-13 t PDLL SLL V T 20405B-14 25 ...

Page 26

... Input, I/ Feedback Registered Output Latched Output t ARR Clock or V Input Latch T Gate 20405B- – Output Disable/Enable MACH211SP-7/10/12/15/ WIGL 20405B-16 Input Latch Gate Width t APW APR V 20405B-18 Asynchronous Preset 20405B-19 ...

Page 27

... State Permitted Unknown Does Not Center Apply Line is High- Impedance “Off” State Output Test Point Commercial 300 5 pF MACH211SP-7/10/12/15/20 KS000010-PAL 20405B-20 R Measured Output Value 2 1.5 V 390 – ...

Page 28

... All frequencies except f other measured AC parameters. f sured directly. ” CNT. (SECOND CHIP SIR + MACH211SP-7/10/12/15/ type is the MAX + t ). Usually, this mini feedback.” MAX . Because this involves no MAXIR + t SIR HIR + t ). The clock WICL WICH + t ) ...

Page 29

... Min Pattern Data Retention Time DR N Max Reprogramming Cycles parts result, the device can be erased and repro- grammed, a feature which allows 100% testing at the factory. Min Units 10 Years 20 Years 100 Cycles MACH211SP-7/10/12/15/20 Test Conditions Max Storage Temperature Max Operating Temperature Normal Programming Conditions 29 ...

Page 30

... INPUT/OUTPUT EQUIVALENT SCHEMATICS ESD Protection Input 100 k Preload Feedback Circuitry Input I/O MACH211SP-7/10/12/15/20 CC 100 20405B-22 ...

Page 31

... Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met Power-Up Reset Waveform MACH211SP-7/10/12/15/20 can rise to its CC rise must be monotonic. Max Unit 10 s See Switching Characteristics V CC ...

Page 32

... Boston, MA 02118 (800) 777-2432 or (617) 422-2793 32 (subject to change) SOFTWARE DEVELOPMENT SYSTEMS Design Center/AMD Software PROsynthesis/AMD Software Verilog, LeapFrog, RapidSim Simulators PLDesigner™-XL Software MultiSIM Interactive Simulator MACH211SP-7/10/12/15/20 ® MACHXL Software Ver. 3.0 AMD-ABEL Software Data I/O MACH Fitters PROdeveloper/AMD Software PLD™ Designer Ver. 9504 ABEL™ ...

Page 33

... Advanced Micro Devices is not responsible for any information relating to the products of third parties. The inclusion of such information is not a representation nor an endorsement by AMD of these products. (subject to change) (continued) SOFTWARE DEVELOPMENT SYSTEMS (Requires PROSim Simulator MACH Fitter) TEST GENERATION SYSTEM ATGEN™ Test Generation Software MACH211SP-7/10/12/15/20 ViewPLD or PROPLD ViewSim Simulator PLDCheck 90 33 ...

Page 34

... No. 1, Alley 8, Lane 45 Bao Shing Rd., Shin Diau Taipei, Taiwan 2-917-3005 34 (subject to change) PROGRAMMER CONFIGURATION BP1148 UniSite™ Model 2900 ALL-07 Sprint Turpro-1 MACH211SP-7/10/12/15/20 Pilot U84 BP1200 BP2100 Model 3900 AutoSite FLEX-700 ALLPRO™-88 Expert Multisite Stag Quazar Stag Eclipse FX TX ...

Page 35

... Logical Systems Corp. P.O. Box 6184 Syracuse, NY 13217-6184 (315) 478-0722 Procon Technologies, Inc. 1333 Lawrence Expwy, Suite 207 Santa Clara, CA 95051 (408) 246-4456 PROGRAMMER CONFIGURATION JTAG PROG MACHpro (subject to change) PART NUMBER Contact Manufacturer Contact Manufacturer Contact Manufacturer Contact Manufacturer Contact Manufacturer MACH211SP-7/10/12/15/20 35 ...

Page 36

... REF .032 TOP VIEW * For reference only. BSC is an ANSI standard for Basic Space Centering. 36 .062 .083 .042 .056 .009 .015 .090 .120 .165 .180 SIDE VIEW MACH211SP-7/10/12/15/20 .500 .590 REF .630 .013 .021 SEATING PLANE 16-038-SQ PL 044 DA78 6-28-94 ae ...

Page 37

... AMD, the AMD logo, MACH, and PAL are registered trademarks of Advanced Micro Devices, Inc. Bus-Friendly is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 9.80 10.20 11.80 12.20 11 – 13 1.20 MAX 11 – 13 0.80 BSC 0.30 0.45 MACH211SP-7/10/12/15/20 11.80 12.20 9.80 10.20 16-038-PQT-2 PQT 44 7-11- ...

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