MC146818AP Motorola, MC146818AP Datasheet
MC146818AP
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MC146818AP Summary of contents
Page 1
... CMOS I “’~:$ u“ CASE 623 PIN ASSIGNMENT ~vDD ‘oT Oscl [ SQW 0SC2 [ ADO [ 4 21 JCKOUT AD1 [ CKFS AD2 [ l~Q AD3 [ RESET AD4 [ STBY AD5 c g AD6 [ Rl~ AD7 [ Vss [ )MOTOROLAINC ADI-1026 ...
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... Current ~rai~~r Pin Excluding Vmi,a%q,.vs s Op&~~~&Temperature Range ‘~%$~6818A TA ‘<@c146818AC Storage Temperature Range Tstg THERMAL CHARACTERISTICS Characteristic Thermal Resistance Plastic Cerdlp Ceramic MOTOROLA @ FIGURE 1 – BLOCK DIAGRAM v VSS) to Value Unit v –0.3 to +8.0 V5S– O.5 to VDD+O – ...
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ELECTRICAL CHARACTERISTICS ( Characteristics Frequency of Operation Output Voltage lLoad< lOpA IDD – Bus Idle CKOUT=fosc, CL= 15 pF; SOW Disabled, STBY=O.2 fosc=32.76B kHz IDD – Quiescent fosc= DC; OSC1 = DC; All Other V; lnpUtS=vDD–0.2 ...
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... Hold Time after AS/ALE Fall 33 NOTE: Designations E, ALE, ~, and ~R refer to signals from alternative * Refer to IMPORTANT NOTICES appearing V, VLOW=O.8 Note: VHIGH=VDD–2.O VHIGH=2.O V, VLOW=O.5 V, for VDD=3.O MOTOROLA @ Vnn=3.O ti;F Load Symbol Min Max 5000 tcvc High PWEL lm Low PWEH 15m — tr, tf tRWH ...
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... C= (Chip Select) STBY ADO-AD7 (Address/ Data Bus) FIGURE 4 – BUS WRITE TIMINti?@PETITOR ADO-AD7 (Address/ Data Bus) Note: VHIGH=VDD-2.O V, VLOW=O.8 V, for VDD=5.O VHIGH=2.O V, VLOW=O.5 V, for VDD=3.O MOTOROLA @ MULTIPLEXED I IL MULTIPLEXED * Address Valid < 10% for outputs only. V for outputs only. ...
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... Description I Oscillator Startu Reset Pulse Width Reset Delay Time DA,.,-. C---- D, ,1-- !AI; A+L DS RESET ITQ All Outputs Except OSC2 (See Figure 10) m MOTOROLA — CHARACTERISTICS (VSS=O Vdc, TA TH) VDD=3.O Vdc I Symbol I Min Max Unit I I lTBDlms]– ltRrl– — ...
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... VDD Pin ~~ Ov RESET Pin CKOUT Pin VDD Pin Ov PS Pin . The VRT bit is set to a ,1’, by reading Register d. The VRT bit mn only be cleared by pulling the PS pin low (see REGISTER D ($OD)). ~ MOTOROLA @ FIGURE 7 – POWER-UP Semiconductor Products Inc. 7 ...
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... CHIP SELECT, INPUT 8.192 kHz The chip-select (C~) signal must be asserted (low) for a bus cycle in which the MC146818A accessed not latched and must be stable during DS and AS (Motorola case of MOTEL) and during ~D and ~R. take place without Register A, as place within the MC146818A. When C% is not used, it should be grounded ...
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... FIGURE 9 – EXTERNAL TIME-BASE 4.1%304 MHz or 1.W576 MHz 32.7:; kHz 4.1- MHz fow RS (Maximum (Maximum 0.012 Cin/Cout 15-30 pF — MOTOROLA @ CONNECTION VDD $ Optional (VDD–1 Oscl 3 (Open)<— OSC2 L MC146818A ,.. ,!~.- OSC2 MC146818A 1.046576 MHz 32.7@ kHz 700 n ...
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... RAM, time registers, and calendar guaranteed. PS must go high after powerup VRT bit to be set by a read of register D, m MOTOROLA FIGURE 12–TYPICAL that The ~Q bit causing the in- bit program normally inter- the ~Q level is devices one pullup at the calendar, ...
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... The contents of th.$,~@&~”~, calendar, and alarm bytes may be either bi.~r~.,~~ decimal (BCD). — Bvtes User RAM 63 (M) MOTOROLA to keep Before initializing systems, a Register B should power supply, updates from the transition from tions in the selected backed-up the format minimize power ...
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... Writing a “1” interrupt-enable when the event occurs. A “U’ in that interrupt to be initiated the interrupt-enable bit prohibits the IRQ pin from being asserted due to the interrupt cause. MOTOROLA @ AND ALARM DATA Decimal Range Range Binary Data Mode BCD Data Mode ...
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... L&’’” MOTOROLA operating time base, the first update cycle is one-half second later. The divider-control testing the MC146818A. corresponding SQUARE-WAVE which is Fifteen of the 22 divider taps are made available to a bit may be set. 1-of-1 5 selector as shown in Figure 1. The first purpose of selecting a divider tap is to generate a square-wave output signal at the SQW pin ...
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... Periodic Interrupt Time Interval (500 ms, 250 ms, 125 ms, 62,5 ms, etc. per Table 5) tuc = Update Cycle Time ( tBUC = Delay Time Before Update Cycle (2M KS) m MOTOROLA complete, the output will be undefined. gress (UIP) status bit is set during the interval. pin to be triggered ...
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... SET – When the SET bit is a “O’, the update cycle func- tions normally by advancing the counts once-per-second. When the SET bit is written to a “1”, 1— @ MOTOROLA progress is aborted and the program may initialize the time and calendar bytes without an update occurring in the midst of initializing. by RESET or internal functions PIE – read/write ...
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... MOTOROLA MC6801 MC146B05E2 Address Decode High-Speed Silicon- I Gate CMOS or TTL I Address Decoding I L—— —_ —__ MOTOROLA @ pin is driven low – The remaining They cannot bit on The MC146818A sors which generate Figures 16 and 17 show independent signal processors. ...
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... Decode FIGURE 18 – MC CMOS MULTIPLEXED M C14@05E2 @ti’$~~?exed Address/Data Oscl ~_______-----___2l I I This illustrates the use of CMOS gating for address decoding. MOTOROLA @ MULTIPL~ED BUS MICROPROCESSORS m l~Q R ~~8A INTERFACE WITH MC148805W MICROP~@~,SOR WITH SLOW ADDRESSING AS RIW RESET MC146818A ...
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... SINGLE CHIP MICROCOMPUTER — M C3870 M C6805 MC 146805 S2000 8021 L——— —— * NOTE: C= can be controlled by a port pin (ifJav}#able). *. ~ADo-AD7 DO-D7 MOTOROLA @ 4. 193W MHz (Tvp) a <$ AS Vss Semiconductor Products Inc. 18 fl_ Power Failure STBY Circuit (See STBY Description) — ...
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... FIGURE 21 – SUBROUTINE THE MCl@18A WITH A NON-MULTIPLIED READ STA RTC LDAB RTC+ 1 RTS STA RTC WRITE STAB RTC+ 1 RTS B MOTOROLA FOR READING AND WRITING BUS Semiconductor Products Inc. 19 ...
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... Inc. Motorola, Inc Equal Employment registered trademarks of Motorola, Semiconductor Products inc. 3501 ED BLUESTEIN BLVD., AUSTIN< TEXAS 78721 . A SUBSIDIARY OF MOTOROLA INC. reliability, function or design. Motorola does neither does it convey any license under its ...