MC68020FE20 Motorola, MC68020FE20 Datasheet
MC68020FE20
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MC68020FE20 Summary of contents
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... Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold ...
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... In particular, assertion and assert refer to a signal that is active or true; negation and negate indicate a signal that is inactive or false. These terms are used independently of the voltage level (high or low) that they represent. MOTOROLA PREFACE NOTE M68020 USER’S MANUAL iii ...
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... Transfer Size Signals (SIZ1, SIZ0) ......................................................... 3-2 3.6 Asynchronous Bus Control Signals ......................................................... 3-4 3.7 Interrupt Control Signals.......................................................................... 3-5 3.8 Bus Arbitration Control Signals ............................................................... 3-6 3.9 Bus Exception Control Signals ................................................................ 3-6 3.10 Emulator Support Signal ......................................................................... 3-7 3.11 Clock (CLK) ............................................................................................. 3-7 MOTOROLA Title Section 1 Introduction Section 2 Processing States Section 3 Signal Description M68020 USER’S MANUAL UM Rev 1 Page Number vii ...
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... Interrupt Acknowledge Cycle—Terminated Normally ...................... 5-45 5.4.1.2 Autovector Interrupt Acknowledge Cycle ......................................... 5-48 5.4.1.3 Spurious Interrupt Cycle .................................................................. 5-48 5.4.2 Breakpoint Acknowledge Cycle ........................................................... 5-50 5.4.3 Coprocessor Communication Cycles .................................................. 5-53 5.5 Bus Exception Control Cycles................................................................. 5-53 5.5.1 Bus Errors ........................................................................................... 5-55 viii Title Section 4 On-Chip Cache Memory Section 5 Bus Operation M68020 USER’S MANUAL UM Rev.1.0 Page Number MOTOROLA ...
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... Multiple Exceptions.............................................................................. 6-17 6.1.12 Return from Exception ......................................................................... 6-19 6.2 Bus Fault Recovery ................................................................................. 6-21 6.2.1 Special Status Word (SSW)................................................................. 6-21 6.2.2 Using Software to Complete the Bus Cycles ....................................... 6-23 6.2.3 Completing the Bus Cycles with RTE .................................................. 6-24 6.3 Coprocessor Considerations ................................................................... 6-25 6.4 Exception Stack Frame Formats ............................................................. 6-25 MOTOROLA Title Section 6 Exception Processing M68020 USER’S MANUAL UM Rev 1 Page Number ix ...
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... Coprocessor Format Words............................................................. 7-18 7.2.3.2.1 Empty/Reset Format Word ........................................................... 7-18 7.2.3.2.2 Not-Ready Format Word .............................................................. 7-19 7.2.3.2.3 Invalid Format Word ..................................................................... 7-19 7.2.3.2.4 Valid Format Word ....................................................................... 7-20 7.2.3.3 Coprocessor Context Save Instruction ............................................ 7-20 7.2.3.3.1 Format .......................................................................................... 7-20 7.2.3.3.2 Protocol ........................................................................................ 7-21 7.2.3.4 Coprocessor Context Restore Instruction ........................................ 7-22 7.2.3.4.1 Format .......................................................................................... 7-22 7.2.3.4.2 Protocol ........................................................................................ 7-23 7.3 Coprocessor Interface Register Set ........................................................ 7-24 x Title Section 7 M68020 USER’S MANUAL UM Rev.1.0 Page Number MOTOROLA ...
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... Take Midinstruction Exception Primitive .............................................. 7-47 7.4.20 Take Postinstruction Exception Primitive ............................................ 7-48 7.5 Exceptions ............................................................................................... 7-49 7.5.1 Coprocessor-Detected Exceptions ...................................................... 7-49 7.5.1.1 Coprocessor-Detected Protocol Violations ...................................... 7-50 7.5.1.2 Coprocessor-Detected Illegal Command or Condition Words ......... 7-51 7.5.1.3 Coprocessor Data-Processing-Related Exceptions ......................... 7-51 7.5.1.4 Coprocessor System-Related Exceptions ....................................... 7-51 7.5.1.5 Format Errors ................................................................................... 7-52 7.5.2 Main-Processor-Detected Exceptions ................................................. 7-52 7.5.2.1 Protocol Violations ........................................................................... 7-52 7.5.2.2 F-Line Emulator Exceptions ............................................................. 7-54 MOTOROLA Title M68020 USER’S MANUAL UM Rev 1 Page Number xi ...
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... Bit Field Manipulation Instructions....................................................... 8-36 8.2.15 Conditional Branch Instructions........................................................... 8-37 8.2.16 Control Instructions.............................................................................. 8-38 8.2.17 Exception-Related Instructions ............................................................ 8-39 8.2.18 Save and Restore Operations ............................................................. 8-40 9.1 Floating-Point Units ................................................................................. 9-1 9.2 Byte Select Logic for the MC68020/EC020............................................. 9-5 9.3 Power and Ground Considerations ......................................................... 9-9 xii Title Section 8 Instruction Execution Timing Section 9 Applications Information M68020 USER’S MANUAL UM Rev.1.0 Page Number MOTOROLA ...
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... MC68EC020 RP Suffix—Pin Assignment.......................................... 11-8 11.2.8 MC68EC020 RP Suffix—Package Dimensions ................................. 11-9 11.2.9 MC68EC020 FG Suffix—Pin Assignment.......................................... 11-10 11.2.10 MC68EC020 FG Suffix—Package Dimensions ................................. 11-11 Interfacing an MC68EC020 to a DMA Device That Supports a Three-Wire Bus Arbitration Protocol MOTOROLA Title Section 10 Electrical Characteristics Section 11 Appendix A M68020 USER’S MANUAL UM Rev 1 Page Number ...
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... Byte Enable Signal Generation for 16- and 32-Bit Ports.................................. 5-23 5-19 Long-Word Read Cycle Flowchart ................................................................... 5-26 5-20 Byte Read Cycle Flowchart .............................................................................. 5-27 5-21 Byte and Word Read Cycles—32-Bit Port ....................................................... 5-28 5-22 Long-Word Read—8-Bit Port ........................................................................... 5-29 5-23 Long-Word Read—16- and 32-Bit Ports .......................................................... 5-30 xiv Title M68020 USER’S MANUAL UM Rev.1.0 Page Number MOTOROLA ...
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... Interrupt Exception Processing Flowchart ........................................................ 6-15 6-6 Breakpoint Instruction Flowchart ...................................................................... 6-18 6-7 RTE Instruction for Throwaway Four-Word Frame .......................................... 6-20 6-8 Special Status Word Format ............................................................................ 6-22 7-1 F-Line Coprocessor Instruction Operation Word.............................................. 7-3 7-2 Asynchronous Non-DMA M68000 Coprocessor Interface Signal Usage ......... 7-5 7-3 MC68020/EC020 CPU Space Address Encodings .......................................... 7-6 MOTOROLA Title M68020 USER’S MANUAL UM Rev 1 Page Number xv ...
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... Operand Format in Memory for Transfer to –(An) ........................................... 7-44 7-39 Transfer Status Register and ScanPC Primitive Format.................................. 7-44 7-40 Take Preinstruction Exception Primitive Format .............................................. 7-45 7-41 MC68020/EC020 Preinstruction Stack Frame ................................................. 7-46 7-42 Take Midinstruction Exception Primitive Format .............................................. 7-47 7-43 MC68020/EC020 Midinstruction Stack Frame ................................................. 7-47 7-44 Take Postinstruction Exception Primitive Format............................................. 7-48 xvi Title M68020 USER’S MANUAL UM Rev.1.0 Page Number MOTOROLA ...
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... Access Level Control Bus Registers ................................................................ 9-17 10-1 Drive Levels and Test Points for AC Specifications ....................................... 10-6 10-2 Clock Input Timing Diagram ........................................................................... 10-7 10-3 Read Cycle Timing Diagram .......................................................................... 10-11 10-4 Write Cycle Timing Diagram........................................................................... 10-12 10-5 Bus Arbitration Timing Diagram ..................................................................... 10-13 A-1 Bus Arbitration Circuit—MC68EC020 (Two-Wire) to DMA (Three-Wire) ......... A-1 MOTOROLA Title M68020 USER’S MANUAL UM Rev 1 Page Number xvii ...
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... Valid Effective Address Field Codes ................................................................ 7-36 7-5 Main Processor Control Register Select Codes............................................... 7-41 7-6 Exceptions Related to Primitive Processing .................................................... 7-53 8-1 Examples 1–4 Instruction Stream Execution Comparison ............................... 8-8 8-2 Instruction Timings from Timing Tables ........................................................... 8-11 8-3 Observed Instruction Timings .......................................................................... 8-11 xviii LIST OF TABLES Title M68020 USER’S MANUAL UM Rev.1.0 Page Number MOTOROLA ...
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... Less Than or Equal to the CPU Maximum Frequency Rating........................ 9-14 9-6 Access Status Register Codes......................................................................... 9-18 10-1 vs. Airflow—MC68020 CQFP Package ................................................... 10-3 JA 10-2 Power vs. Rated Frequency (at T 10-3 Temperature Rise of Board vs. P 10-4 vs. Airflow—MC68EC020 PQFP Package .............................................. 10-4 JA MOTOROLA Title Maximum = 110 C) ................................. 10-3 J —MC68020 CQFP Package ................... 10-3 D M68020 USER’S MANUAL UM Rev 1 Page Number xix ...
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... SP — Stack Pointer SR — Status Register SSP — Supervisor Stack Pointer SSW — Special Status Word UMB — Upper Middle Byte USP — User Stack Pointer VBR — Vector Base Register VLSI — Very Large Scale Integration MOTOROLA M68020 USER’S MANUAL v ...
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... SECTION 1 INTRODUCTION The MC68020 is the first full 32-bit implementation of the M68000 family of microprocessors from Motorola. Using VLSI technology, the MC68020 is implemented with 32-bit registers and data paths, 32-bit addresses, a rich instruction set, and versatile addressing modes. The MC68020 is object-code compatible with earlier members of the M68000 family and ...
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... Direct Addressing Range for the MC68020 • 16-Mbyte Direct Addressing Range for the MC68EC020 • Selection of Processor Speeds for the MC68020: 16.67, 20, 25, and 33.33 MHz • Selection of Processor Speeds for the MCEC68020: 16.67 and 25 MHz A block diagram of the MC68020/EC020 is shown in Figure 1- M68020 USER’S MANUAL MOTOROLA ...
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... ADDRESS PADS ADDRESS BUS BUS CONTROLLER WRITE PENDING PREFETCH PENDING BUFFER BUFFER MICROBUS CONTROL LOGIC BUS CONTROL SIGNALS * 24-Bit for MC68EC020 Figure 1-1. MC68020/EC020 Block Diagram MOTOROLA INSTRUCTION PIPE STAGE STAGE STAGE INSTRUCTION CACHE EXECUTION UNIT PROGRAM DATA ADDRESS COUNTER SECTION ...
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... A7–A0) may be used as index registers. The PC contains the address of the next instruction to be executed by the MC68020/EC020. During instruction execution and exception processing, the processor automatically increments the contents of the PC or places a new value in the PC, as appropriate M68020 USER’S MANUAL MOTOROLA ...
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... Figure 1-2. User Programming Model MOTOROLA M68020 USER’S MANUAL DATA REGISTERS ADDRESS A3 REGISTERS USER STACK A7 (USP) POINTER 0 PROGRAM PC COUNTER 0 CONDITION CODE CCR REGISTER 1- 5 ...
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... Figure 1-3. Supervisor Programming Model Supplement (CCR) M68020 USER’S MANUAL 0 INTERRUPT STACK A7' (ISP) POINTER 0 MASTER STACK A7'' (MSP) POINTER 0 STATUS SR REGISTER 0 VECTOR BASE VBR REGISTER ALTERNATE SFC FUNCTION CODE DFC REGISTERS 0 CACHE CONTROL CACR REGISTER 0 CACHE ADDRESS CAAR REGISTER MOTOROLA ...
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... Registers SFC and DFC are used by certain instructions to explicitly specify the function codes for operations. The CACR controls the on-chip instruction cache of the MC68020/EC020. The CAAR stores an address for cache control functions. MOTOROLA SYSTEM BYTE (CONDITION CODE REGISTER) 13 ...
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... The register indirect addressing modes have postincrement, predecrement, displacement, and index capabilities. The PC modes have index and offset capabilities. Both modes are extended to provide indirect reference through memory. In addition to these addressing modes, many instructions implicitly specify the use of the CCR, stack pointer, and/or PC M68020 USER’S MANUAL MOTOROLA ...
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... PC = Program Counter <data> = Immediate value bits ( ) = Effective Address [ ] = Use as indirect access to long-word address. MOTOROLA Table 1-1. Addressing Modes Addressing Modes SCALE, where SIZE (indicates index register * M68020 USER’S MANUAL Syntax Dn An (An) (An)+ –(An) ...
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... When the bus error handler has completed execution, it returns control to the program that was executing when the error was detected, reruns the faulted bus cycle (when required), and continues the suspended instruction M68020 USER’S MANUAL MOTOROLA ...
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... LSL, LSR Logical Shift Left and Right MOVE Move MOVEA Move Address MOVE CCR Move Condition Code Register MOVE SR Move Status Register MOTOROLA Table 1-2. Instruction Set Mnemonic MOVE USP Move User Stack Pointer MOVEC Move Control Register MOVEM Move Multiple Registers MOVEP ...
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... The cache holding register provides instruction words to the pipe regardless of whether the instruction cache is enabled or disabled M68020 USER’S MANUAL MOTOROLA ...
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... To exploit these locality characteristics, the MC68020/EC020 contains an on-chip instruction cache. The cache improves the overall performance of the system by reducing the number of bus cycles required by the processor to fetch information from memory and by increasing the bus bandwidth available for other bus masters in the system. MOTOROLA INSTRUCTION PIPE STAGE STAGE D C Figure 1-5 ...
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... Only an external reset can restart a halted processor. (When the processor executes a STOP instruction special type of normal processing state—one without bus cycles stopped, not halted.) MOTOROLA NOTE M68020 USER’S MANUAL ...
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... When the M-bit is clear, the MC68020/EC020 is in the interrupt mode of the supervisor privilege level, and operation is the same as supervisor mode in the MC68000, MC68HC001, MC68008, and MC68010. (The processor is in this mode after a reset operation.) All SSP references access the ISP in this mode M68020 USER’S MANUAL MOTOROLA ...
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... After these instructions execute, the instruction pipeline is flushed and is refilled from the appropriate address space. The RTE instruction returns to the program that was executing when the exception occurred. It restores the exception stack frame saved on the supervisor stack. If the frame MOTOROLA M68020 USER’S MANUAL 2- 3 ...
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... Address space 3 is reserved for user definition; 0 and 4 are reserved for future use by Motorola. The memory locations of user program and data accesses are not predefined; neither are the locations of supervisor data space. During reset, the first two long words beginning at memory location zero in the supervisor program space are used for processor initialization ...
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... Since the VBR provides the base address of the vector table, the vector table can be located anywhere in memory; it can even be dynamically relocated for each task that is executed by an operating system. Details of exception processing are provided in Section 6 Exception Processing, and Table 6-1 lists the exception vector assignments. MOTOROLA M68020 USER’S MANUAL 2- 5 ...
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... Figure 2-1. Refer to Section 6 Exception Processing for a complete list of exception stack frames. SSP Figure 2-1. General Exception Stack Frame STATUS REGISTER PROGRAM COUNTER FORMAT VECTOR OFFSET ADDITIONAL PROCESSOR STATE INFORMATION ( WORDS, IF NEEDED) M68020 USER’S MANUAL 0 MOTOROLA ...
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... These terms are used independently of the voltage level (high or low) that they represent. FUNCTION CODES ADDRESS BUS DATA BUS TRANSFER SIZE ASYNCHRONOUS BUS CONTROL EMULATOR SUPPORT Figure 3-1. Functional Signal Groups MOTOROLA NOTE IPL0 FC2–FC0 IPL1 ** A31–A0 IPL2 D31–D0 * ...
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... These three-state outputs indicate the number of bytes remaining to be transferred for the current bus cycle. Signals A1, A0, DSACK1, DSACK0, SIZ1, and SIZ0 define the number of bits transferred on the data bus. Refer to Section 5 Bus Operation for more information on SIZ1 and SIZ0 and their use in dynamic bus sizing M68020 USER’S MANUAL MOTOROLA ...
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... V Ground GND * This signal is implemented in the MC68020 and not implemented in the MC68EC020. MOTOROLA Table 3-1. Signal Index 3-bit function code used to identify the address space of each bus cycle. 32-bit address bus 24-bit address bus 32-bit data bus used to transfer 8, 16, 24 bits of data per bus cycle ...
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... During a write cycle, DS indicates that the MC68020/EC020 has placed valid data on the bus. During two-clock synchronous write cycles, the MC68020/EC020 does not assert DS . Refer to Section 5 Bus Operation for more information about the relationship bus operation M68020 USER’S MANUAL MOTOROLA ...
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... Processing for interrupt information. Also, refer to Section 5 Bus Operation for bus information related to interrupts. IPEND is not implemented in the MC68EC020. Autovector (AVEC) This input signal indicates that the MC68020/EC020 should generate an automatic vector during an interrupt acknowledge cycle. Refer to Section 5 Bus Operation for more information about automatic vectors. MOTOROLA M68020 USER’S MANUAL 3- 5 ...
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... RESET instruction) resets external devices only; the internal state of the processor is not altered. Refer to Section 5 Bus Operation for a description of reset bus operation and Section 6 Exception Processing for information about the reset exception M68020 USER’S MANUAL MOTOROLA ...
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... The ground connections are similarly grouped. Section 11 Ordering Information and Mechanical Data describes the groupings of V connections, and Section 9 Applications Information describes a typical power supply interface. MOTOROLA power supply, positive with respect to CC M68020 USER’S MANUAL and ground ...
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... High Yes High Yes Low No Low No High/Low Yes Low Yes Low Yes Low Yes Low Yes Low — Low — Low No Low — Low — Low No Low — ** Low No ** Low No Low — Low — — — — — — — MOTOROLA ...
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... CPU. Instruction prefetches are normally requested from sequential memory addresses except when a change of program flow occurs (e.g., a branch taken) or when an instruction is executed that can modify the SR. In these cases, the instruction pipe is automatically flushed and refilled. MOTOROLA M68020 USER’S MANUAL 4- 1 ...
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... TAG WORD TAG V WORD VALID ENTRY HIT COMPARATOR LINE HIT NOTE M68020 USER’S MANUAL INDEX SELECT WORD REPLACEMENT DATA TO INSTRUCTION PATH CACHE CONTROL MOTOROLA ...
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... The CACR, shown in Figure 4- 32-bit register than can be written or read by the MOVEC instruction or indirectly modified by a reset. Four of the bits (3–0) control the instruction cache. Bits 31–4 are reserved for Motorola definition. They are read as zeros and are ignored when written. For future compatibility, writes should not set these bits. ...
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... Figure 4-3. Cache Address Register Bits 31–8, 1, and 0—Reserved These bits are reserved for use by Motorola. Index Field The index field contains the address for the “clear cache entry” operations. The bits of this field, which correspond to A7–A2, specify the index and a long word of a cache line. ...
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... The bus operates in an asynchronous mode for any port width. The bus and control input signals are internally synchronized to the MC68020/EC020 clock, introducing a delay. This delay is the time period required for the MC68020/EC020 to sample an input signal, synchronize the input to the internal clocks of the processor, and determine whether the MOTOROLA M68020 USER’S MANUAL 5- 1 ...
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... R/W outputs. However, if the MC68020/EC020 finds the required instruction in the on- chip cache, the processor aborts the cycle before asserting the AS.The assertion of AS ensures that the cycle has not been aborted by these internal conditions. 5-2 SYNC DELAY SAMPLE WINDOW Figure 5-2. Input Sample Window M68020 USER’S MANUAL MOTOROLA ...
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... The FC2–FC0 signals select one of eight address spaces (see Table 2-1) to which the address applies. Five address spaces are presently defined. Of the remaining three, one is reserved for user definition, and two are reserved by Motorola for future use. FC2–FC0 are valid while AS is asserted. ...
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... Again, the BERR and HALT signals can be simultaneously asserted in lieu of conjunction with, the DSACK1/DSACK0 signals. Finally, the AVEC signal can be used to terminate interrupt acknowledge cycles, indicating that the MC68020/EC020 should generate a vector number to locate an interrupt handler routine. AVEC is ignored during all other bus cycles. 5-4 M68020 USER’S MANUAL MOTOROLA ...
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... OP0; the least significant byte is OP3. The two bytes of a word- length operand are OP2 (most significant) and OP3. The single byte of a byte-length operand is OP3. These designations are used in the figures and descriptions that follow. MOTOROLA DSACK1/DSACK0 Encodings and Results ...
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... BYTE OPERAND OP1 OP2 1 2 ROUTING AND DUPLICATION D23–D16 D15–D8 BYTE 1 BYTE 2 BYTE 1 16-BIT PORT BYTE 3 8-BIT PORT M68020 USER’S MANUAL 0 OP2 OP3 0 OP2 OP3 7 0 OP3 OP3 3 INTERNAL TO THE MC68020/EC020 D7–D0 EXTERNAL BUS BYTE 3 32-BIT PORT MOTOROLA ...
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... A1 and A0 indicate the byte offset from the base. Table 5-3 lists the encodings of A1 and A0 and the corresponding byte offsets from the long-word base. Table 5-3. Address Offset Encodings Negated Negated Asserted Asserted MOTOROLA SIZ0 Asserted Negated Asserted Negated Long Word A1 ...
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... OP3 OP2 OP3 OP2 OP2 OP2 OP3 OP2 OP3 OP2 OP2 OP2 OP2 OP1 OP2 OP1 OP3 OP1 OP1 OP2 OP1 OP2 OP1 OP1 OP1 OP1 OP3 OP0 OP1 OP0 OP2 OP0 OP0 OP1 OP0 OP1 OP0 OP0 OP0 OP0 MOTOROLA ...
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... Due to the current implementation, this byte is output but never used Don't care NOTE: The OP tables on the external data bus refer to a particular byte of the operand that is written on that section of the data bus. MOTOROLA Multiplexer—Write Cycles External Data Bus Size Address D31– ...
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... D31 DATA BUS WORD MEMORY MSB OP0 OP2 Figure 5-5. Long-Word Operand Write to Word Port Example 5-10 LONG-WORD OPERAND OP1 OP2 D16 MC68020/EC020 LSB SIZ1 SIZ0 A1 OP1 OP3 M68020 USER’S MANUAL 0 OP3 MEMORY CONTROL A0 DSACK1 DSACK0 MOTOROLA ...
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... DSACK0 ** DBEN D31–D24 D23–D16 * For the MC68EC020, A23–A2. ** This signal does not apply to the MC68EC020. Figure 5-6. Long-Word Operand Write to Word Port Timing MOTOROLA OP0 OP1 WORD WRITE LONG-WORD OPERAND WRITE TO 16-BIT PORT M68020 USER’S MANUAL ...
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... D31 DATA BUS D24 BYTE MEMORY Figure 5-7. Word Operand Write to Byte Port Example 5-12 WORD OPERAND 0 OP2 OP3 MC68020/EC020 SIZ1 SIZ0 A1 A0 OP2 OP3 M68020 USER’S MANUAL MEMORY CONTROL DSACK1 DSACK0 MOTOROLA ...
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... DBEN D31–D24 D23–D16 D15–D8 D7–D0 * For the MC68EC020, A23–A2. ** This signal does not apply to the MC68EC020. Figure 5-8. Word Operand Write to Byte Port Timing MOTOROLA BYTE WRITE WORD OPERAND WRITE M68020 USER’S MANUAL S2 S4 BYTE WRITE ...
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... Figure 5-9. Misaligned Long-Word Operand Write to Word Port Example 5-14 LONG-WORD OPERAND OP1 OP2 D16 MC68020/EC020 SIZ1 SIZ0 LSB A2 A1 OP0 OP2 XXX M68020 USER’S MANUAL 0 OP3 MEMORY CONTROL A0 DSACK1 DSACK0 MOTOROLA ...
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... DSACK0 ** DBEN D31–D24 D23–D16 D15–D8 D7–D0 BYTE WRITE * For the MC68EC020, A23–A2. This signal does not apply to the MC68EC020. Figure 5-10. Misaligned Long-Word Operand Write to Word Port Timing MOTOROLA OP0 OP1 OP0 OP2 OP1 OP1 OP2 ...
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... Word Port Example 0 OP3 D16 MC68020/EC020 LSB SIZ1 SIZ0 A2 OP2 XXX M68020 USER’S MANUAL 0 MEMORY CONTROL MC68020/EC020 A1 A0 DSACK1 DSACK0 MEMORY CONTROL A1 A0 DSACK1 DSACK0 MOTOROLA ...
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... DBEN D31–D24 D23–D16 D15–D8 D7–D0 * For the MC68EC020, A23–A2. ** This signal does not apply to the MC68EC020. Figure 5-13. Misaligned Word Operand Write to Word Port Timing MOTOROLA OP2 OP2 OP3 OP2 WORD WRITE WORD OPERAND WRITE TO A1 M68020 USER’ ...
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... XXX OP2 OP3 D0 LMB LSB SIZ1 SIZ0 A2 XXX OP0 OP3 XXX to Long-Word Port Example M68020 USER’S MANUAL MEMORY CONTROL A0 DSACK1 DSACK0 MC68020/EC020 MEMORY CONTROL A1 A0 DSACK1 DSACK0 MOTOROLA L L ...
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... DSACK0 ** DBEN D31–D24 D23–D16 D15–D8 D7–D0 * For the MC68EC020, A23–A2. ** This signal does not apply to the MC68EC020. Figure 5-16. Misaligned Long-Word Operand Write MOTOROLA OP0 OP0 OP1 OP0 BYTE WRITE LONG-WORD OPERAND WRITE to Long-Word Port Timing M68020 USER’ ...
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... LMB LSB XXX OP0 OP3 XXX from Long-Word Port Example Number of Bus Cycles (Data Port Size = 32 Bits:16 Bits:8 Bits) A1 1:2:4 N/A 1:1:1 1:1:1 1:1:2 1:2:2 1:2:4 2:3:4 M68020 USER’S MANUAL 0 MC68020/EC020 MEMORY CONTROL SIZ1 SIZ0 DSACK1 N/A N/A 1:1:1 1:1:1 1:1:2 2:2:2 2:2:4 2:3:4 MOTOROLA DSACK0 L L ...
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... These enable or strobe signals select only the bytes required for write or read cycles. The other bytes are not selected, which prevents incorrect accesses in sensitive areas such as I/O. MOTOROLA M68020 USER’S MANUAL 5- 21 ...
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... B M68020 USER’S MANUAL D15–D8 D7–D0 — — — — — — L — W — — — — — — — — L MOTOROLA ...
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... A0 A1 SIZ0 SIZ1 R/W Figure 5-18. Byte Enable Signal Generation for 16- and 32-Bit Ports MOTOROLA UUD = UPPER UPPER DATA (32-BIT PORT) UMD = UPPER MIDDLE DATA (32-BIT PORT) LMD = LOWER MIDDLE DATA (32-BIT PORT) LLD = LOWER LOWER DATA (32-BIT PORT UPPER DATA (16-BIT PORT) ...
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... If the assertion of DSACK1/DSACK0 is recognized on a particular falling edge of the clock, valid data is latched into the processor (for a read cycle) on the next falling clock edge provided the data meets the data setup time (parameter #27). In this case, parameter #31 5-24 DSACK1 DSACK0 / M68020 USER’S MANUAL MOTOROLA ...
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... Section 2 Processing States. The clock cycles used in the descriptions and timing diagrams of data transfer cycles are independent of the clock frequency. Bus operations are described in terms of external bus states. MOTOROLA M68020 USER’S MANUAL 5- 25 ...
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... This step does not apply to the MC68EC020. For the MC68EC020, A23–A0. Figure 5-19. Long-Word Read Cycle Flowchart 5-26 EXTERNAL DEVICE 1) DECODE ADDRESS 2) PLACE DATA ON D31–D0 3) ASSERT DSACK1/DSACK0 1) REMOVE DATA FROM D31–D0 2) NEGATE DSACK1/DSACK0 M68020 USER’S MANUAL PRESENT DATA TERMINATE CYCLE MOTOROLA ...
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... START NEXT CYCLE * This step does not apply to the MC68EC020. ** For the MC68EC020, A23–A0. Figure 5-20. Byte Read Cycle Flowchart MOTOROLA EXTERNAL DEVICE 1) DECODE ADDRESS 2) PLACE DATA ON D31–D24 OR (BASED ON A1, A0, AND BUS WIDTH) 3) ASSERT DSACK1/DSACK0 1) REMOVE DATA FROM D31–D0 2) NEGATE DSACK1/DSACK0 M68020 USER’ ...
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... ECS ** OCS AS DS DSACK1 DSACK0 ** DBEN D31–D24 D23–D16 D15–D8 D7–D0 WORD READ * Figure 5-21. Byte and Word Read Cycles—32-Bit Port 5- BYTE OP2 OP3 OP3 BYTE READ M68020 USER’S MANUAL OP3 BYTE READ MOTOROLA ...
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... D31–D24 D23–D16 D15–D8 D7–D0 BYTE READ For the MC68EC020, A23–A2. * This signal does not apply to the MC68EC020. Figure 5-22. Long-Word Read—8-Bit Port MOTOROLA 3-BYTE OP0 OP1 BYTE READ LONG-WORD OPERAND READ FROM 8-BIT PORT M68020 USER’ ...
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... For the MC68EC020, A23–A2. This signal does not apply to the MC68EC020. ** Figure 5-23. Long-Word Read—16- and 32-Bit Ports 5- WORD OP0 OP2 OP1 OP3 WORD READ M68020 USER’S MANUAL LONG WORD OP0 OP1 OP2 OP3 LONG-WORD READ FROM 32-BIT PORT MOTOROLA ...
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... DSACK1 and must remain negated throughout the asynchronous input setup and hold times around the end of S2. If wait states are added, the processor continues to sample the DSACK1/DSACK0 signals on the falling edges of the clock until an assertion is recognized. MOTOROLA M68020 USER’S MANUAL 5- 31 ...
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... (whichever it detects first). The device must remove its data and negate DSACK1/DSACK0 within approximately one clock period after sensing the negation DS. DSACK1/DSACK0 signals that remain asserted beyond this limit may be prematurely detected for the next bus cycle. 5-32 M68020 USER’S MANUAL MOTOROLA ...
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... NEGATE DBEN START NEXT CYCLE * This step does not apply to the MC68EC020. ** For the MC68EC020, A23–A0. Figure 5-24. Write Cycle Flowchart MOTOROLA EXTERNAL DEVICE 1) DECODE ADDRESS 2) STORE DATA FROM D31–D0 3) ASSERT DSACK1/DSACK0 TERMINATE CYCLE 1) NEGATE DSACK1/DSACK0 M68020 USER’S MANUAL ...
Page 81
... AS DS DSACK1 DSACK0 ** DBEN D31–D0 BYTE READ * For the MC68EC020, A23–A2. ** This signal does not apply to the MC68EC020. Figure 5-25. Read-Write-Read Cycles—32-Bit Port 5- WRITE WRITE M68020 USER’S MANUAL READ WITH WAIT STATES MOTOROLA S4 ...
Page 82
... DBEN D31–D24 D23–D16 D15–D8 D7–D0 WORD WRITE * For the MC68EC020, A23–A2. This signal does not apply to the MC68EC020. Figure 5-26. Byte and Word Write Cycles—32-Bit Port MOTOROLA WORD BYTE OP2 OP3 OP2 OP3 BYTE WRITE M68020 USER’ ...
Page 83
... Figure 5-27. Long-Word Operand Write—8-Bit Port 5- 3-BYTE OP1 OP1 OP2 OP3 BYTE WRITE BYTE WRITE LONG-WORD OPERAND WRITE TO 8-BIT PORT M68020 USER’S MANUAL WORD BYTE OP2 OP3 OP3 OP3 OP2 OP3 OP3 OP3 BYTE WRITE MOTOROLA ...
Page 84
... D31–D24 D23–D16 D15–D8 D7–D0 WORD WRITE LONG-WORD OPERAND WRITE TO 16-BIT PORT * For the MC68EC020, A23–A2. ** This signal does not apply to the MC68EC020. Figure 5-28. Long-Word Operand Write—16-Bit Port MOTOROLA WORD OP0 OP2 OP1 OP3 OP2 ...
Page 85
... D23–D16, D15–D8, and D7–D0). SIZ1, SIZ0, A1, and A0 select the bytes of the data bus has not already done so, the device asserts DSACK1/DSACK0 to signal that it has successfully stored the data. 5-38 M68020 USER’S MANUAL MOTOROLA ...
Page 86
... Depending on the compare results of the CAS and CAS2 instructions, the write cycle(s) may not occur. Figure 5- flowchart of the read-modify-write cycle operation. Figure 5- example timing diagram of a TAS instruction specified in terms of clock periods. MOTOROLA M68020 USER’S MANUAL 5- 39 ...
Page 87
... TERMINATE CYCLE 1) NEGATE DSACK1/DSACK0 M68020 USER’S MANUAL A IF CAS2 INSTRUCTION AND ONLY ONE OPERAND READ, THEN OPERANDS DO NOT MATCH, THEN ELSE CAS2 INSTRUCTION AND ONLY ONE OPERAND WRITTEN, THEN ELSE MOTOROLA ...
Page 88
... D15–8 OP3 D7–D0 BERR HALT BG * For the MC68EC020, A23–A2. ** This signal does not apply to the MC68EC020. Figure 5-30. Byte Read-Modify-Write Cycle—32-Bit Port (TAS Instruction) MOTOROLA S6 S8 S10 Si Si OP3 OP3 OP3 OP3 INDIVISIBLE CYCLE M68020 USER’S MANUAL ...
Page 89
... S2. If wait states are added, the processor continues to sample the DSACK1/DSACK0 signals on the falling edges of the clock until one is recognized. State 4 MC68020/EC020—At the end of S4, the processor latches the incoming data. 5-42 M68020 USER’S MANUAL MOTOROLA ...
Page 90
... In addition, ECS (and OCS, if asserted) is negated during S7. MC68EC020—During S7, the processor asserts AS, indicating that the address on the address bus is valid. State 8 MC68020/EC020—During S8, the processor places the data to be written onto the data bus. MOTOROLA M68020 USER’S MANUAL 5- 43 ...
Page 91
... The CPU space type is encoded on A19–A16 during a CPU space operation and indicates the function that the processor is performing. On the MC68020/EC020, four of the encodings are implemented as shown in Figure 5-31. All unused values are reserved by Motorola for future use. 5-44 M68020 USER’S MANUAL ...
Page 92
... Some interrupting devices have programmable vector registers that contain the interrupt vectors for the routines they use. The following paragraphs describe the interrupt acknowledge cycle for these devices. Other interrupting conditions or devices cannot supply a vector number and use the autovector cycle described in 5.4.1.2 Autovector Interrupt Acknowledge Cycle. MOTOROLA ADDRESS BUS ...
Page 93
... INTERRUPTING DEVICE REQUEST INTERRUPT PROVIDE VECTOR INFORMATION 1) PLACE VECTOR NUMBER ON LEAST SIGNIFICANT BYTE OF DATA PORT (DEPENDS ON PORT SIZE) 2) ASSERT DSACK1/DSACK0 ASSERT AVEC FOR AUTOMATIC GENERA- TION OF VECTOR NUMBER 1) REMOVE VECTOR NUMBER FROM DATA BUS 2) NEGATE DSACK1/DSACK0 M68020 USER’S MANUAL OR RELEASE MOTOROLA ...
Page 94
... D7–D0 IPL2–IPL0 ** IPEND READ CYCLE * For the MC68EC020, A23–A4. ** This signal does not apply to the MC68EC020. Figure 5-33. Interrupt Acknowledge Cycle Timing MOTOROLA INTERRUPT LEVEL VECTOR # FROM 8-BIT PORT VECTOR # FROM 16-BIT PORT VECTOR # FROM 32-BIT PORT INTERRUPT ACKNOWLEDGE M68020 USER’ ...
Page 95
... SPURIOUS INTERRUPT CYCLE. When a device does not respond to an interrupt acknowledge cycle with AVEC or DSACK1/DSACK0, the external logic typically returns BERR. In this case, the MC68020/EC020 automatically generates 24, the spurious interrupt vector number. If HALT is also asserted, the processor retries the cycle. 5-48 M68020 USER’S MANUAL MOTOROLA ...
Page 96
... DSACK1 DSACK0 ** DBEN D31–D0 IPL2–IPL0 AVEC READ CYCLE * For the MC68EC020, A23–A4. ** This signal does not apply to the MC68EC020. Figure 5-34. Autovector Operation Timing MOTOROLA INTERRUPT LEVEL INTERRUPT ACKNOWLEDGE AUTOVECTORED M68020 USER’S MANUAL WRITE STACK ...
Page 97
... PLACE LATCHED DATA IN INSTRUCTION PIPELINE 2) CONTINUE PROCESSING 1) INITIATE ILLEGAL INSTRUCTION PROCESSING Figure 5-35. Breakpoint Acknowledge Cycle Flowchart 5-50 1) PLACE REPLACEMENT OPCODE ON DATA BUS 2) ASSERT DSACK1/DTACK0 1) ASSERT BERR TO INITIATE EXCEPTION PROCESSING B SLAVE NEGATES DSACK1/DSACK0 OR BERR M68020 USER’S MANUAL EXTERNAL DEVICE OR MOTOROLA ...
Page 98
... ECS ** OCS AS DS DSACK1 DSACK0 ** DBEN D23–D16 D15–D8 D7–D0 BERR HALT READ CYCLE Figure 5-36. Breakpoint Acknowledge Cycle Timing MOTOROLA (0000) BREAKPOINT ENCODING BREAKPOINT NUMBER WORD BREAKPOINT ACKNOWLEDGE INSTRUCTION WORD FETCH M68020 USER’S MANUAL S0 S2 FETCHED INSTRUCTION ...
Page 99
... DSACK0 ** DBEN D31–D0 BERR HALT READ WITH BERR ASSERTED * For the MC68EC020, A23–A0. ** This signal does not apply to the MC68EC020. Figure 5-37. Breakpoint Acknowledge Cycle Timing (Exception Signaled) 5- M68020 USER’S MANUAL INTERNAL STACK WRITE PROCESSING MOTOROLA ...
Page 100
... Section 10 Electrical Characteristics for timing requirements.) This or some equivalent precaution should be designed into the external circuitry that provides these signals. MOTOROLA M68020 USER’S MANUAL 5- 53 ...
Page 101
... Terminate and take bus error exception, possibly A S deferred Terminate and take bus error exception, possibly N A deferred N/A X Terminate and retry when HALT negated A Terminate and retry when HALT negated M68020 USER’S MANUAL Assertion Results Result MOTOROLA ...
Page 102
... If a bus error occurs on an instruction fetch, the processor does not take the exception until it attempts to use that instruction word. Should an intervening instruction cause a branch or should a task switch occur, the bus error exception does not occur. MOTOROLA M68020 USER’S MANUAL 5- 55 ...
Page 103
... BERR and BR only (HALT must not be included). The bus error handler software should examine the read-modify-write bit in the special status word (refer to Section 6 Exception Processing) and take the appropriate action to resolve this type of fault when it occurs. 5-56 M68020 USER’S MANUAL MOTOROLA ...
Page 104
... D31–D24 D23–D16 D15–D8 D7–D0 BERR HALT READ CYCLE * For the MC68EC020, A23–A20. ** This signal does not apply to the MC68EC020. Figure 5-38. Bus Error without MOTOROLA (0000) BREAKPOINT ENCODING BREAKPOINT NUMBER CPU SPACE WORD BREAKPOINT ACKNOWLEDGE BUS ERROR ...
Page 105
... DSACK0 ** DBEN D31–D0 IPL2–IPL0 BERR HALT WRITE WITH BERR ASSERTED * For the MC68EC020, A23–A0. ** This signal does not apply to the MC68EC020. Figure 5-39. Late Bus Error with 5- INTERNAL PROCESSING DSACK1/DSACK0 M68020 USER’S MANUAL STACK WRITE MOTOROLA ...
Page 106
... OCS AS DS DSACK1 DSACK0 D31–D0 BERR HALT WRITE CYCLE RETRY SIGNALED * For the MC68EC020, A23–A0. ** This signal does not apply to the MC68EC020. MOTOROLA S4 DATA BUS NOT DRIVEN HALT Figure 5-40. Late Retry M68020 USER’S MANUAL RETRY CYCLE 5- 59 ...
Page 107
... A bus cycle that is retried does not constitute a bus error or contribute to a double bus fault. The processor continues to retry the same bus cycle as long as the external hardware requests it. 5-60 M68020 USER’S MANUAL MOTOROLA ...
Page 108
... AS DS DSACK1 DSACK0 ** DBEN D31–D0 BERR HALT READ * For the MC68EC020, A23–A0. ** This signal does not apply to the MC68EC020. Figure 5-41. Halt Operation Timing MOTOROLA S4 HALT (BUS ARBITRATION PERMITTED WHILE THE PROCESSOR IS HALTED) M68020 USER’S MANUAL READ 5- 61 ...
Page 109
... Arbitration. Systems having several devices that can become bus master require external circuitry to assign priorities to the devices, so that when two or more external devices attempt to become bus master at the same time, the one having the highest priority becomes bus master first. 5-62 M68020 USER’S MANUAL MOTOROLA ...
Page 110
... BGACK must be inactive, indicating that no other bus master has claimed ownership of the bus. Figure 5- flowchart of MC68020 bus arbitration for a single device. Figure 5- timing diagram for the same operation. This technique allows processing of bus requests during data transfer cycles. MOTOROLA M68020 USER’S MANUAL 5- 63 ...
Page 111
... NEXT BUS MASTER 2) NEXT BUS MASTER WAITS FOR CURRENT CYCLE TO COMPLETE 3) NEXT BUS MASTER ASSERTS BGACK TO BECOME NEW MASTER 4) BUS MASTER NEGATES BR OPERATE AS BUS MASTER 1) PERFORM DATA TRANSFERS (READ AND WRITE CYCLES) RELEASE BUS MASTERSHIP 1) NEGATE BGACK M68020 USER’S MANUAL MOTOROLA ...
Page 112
... CLK A31–A0 FC2–FC0 SIZ1–SIZ0 R/W ECS OCS AS DS DSACK1 DSACK0 DBEN D31– BGACK PROCESSOR Figure 5-43. MC68020 Bus Arbitration Operation Timing for Single Request MOTOROLA DMA DEVICE M68020 USER’S MANUAL S0 S2 PROCESSOR 5- 65 ...
Page 113
... BGACK is asserted. If another BR is still pending after the assertion of BGACK, another BG is asserted within a few clocks of the negation of the the first BG, as described in 5.7.1.4 Bus Arbitration Control (MC68020). Note that the processor does not perform any external bus cycles before it reasserts BG in this case. 5-66 M68020 USER’S MANUAL MOTOROLA ...
Page 114
... STATE STATE 2 RA R—BUS REQUEST A—BUS GRANT ACKNOWLEDGE G—BUS GRANT T—THREE-STATE CONTROL TO BUS CONTROL LOGIC X—DON'T CARE NOTE: The BG output will not be asserted while RMC is asserted. Figure 5-44. MC68020 Bus Arbitration State Diagram MOTOROLA STATE STATE 3 XA ...
Page 115
... For the duration of this sequence, the MC68020 ignores the BR input. If mastership of the MC68020 bus is required during a read-modify-write operation, BERR must be used to abort the read-modify-write sequence. The bus arbitration sequence while the bus is inactive (i.e., executing internal operations such as a multiply instruction) is shown in Figure 5-45. 5-68 M68020 USER’S MANUAL MOTOROLA ...
Page 116
... FC2–FC0 SIZ1–SIZ0 R/W ECS OCS AS DS DSACK1 DSACK0 DBEN D31– BGACK (ARBITRATION PERMITTED PROCESSOR WHILE THE PROCESSOR IS Figure 5-45. MC68020 Bus Arbitration Operation Timing—Bus Inactive MOTOROLA BUS INACTIVE ALTERNATE MASTER INACTIVE OR HALTED) M68020 USER’S MANUAL S0 PROCESSOR 5- 69 ...
Page 117
... This technique allows processing of bus requests during data transfer cycles. Bus arbitration requests are recognized during normal processing, RESET assertion, HALT assertion, and when the processor has halted due to a double bus fault. 5-70 M68020 USER’S MANUAL MOTOROLA ...
Page 118
... BG is deferred until the bus cycle has begun. BG may be routed through a daisy-chained network or through a specific priority-encoded network. The processor allows any type of external arbitration that follows the protocol. MOTOROLA REQUESTING DEVICE REQUEST THE BUS 1) ASSERT BR ...
Page 119
... CLK A23–A0 FC2–FC0 SIZ1–SIZ0 R DSACK1 DSACK0 D31– PROCESSOR Figure 5-47. MC68EC020 Bus Arbitration Operation Timing for Single Request 5-72 DMA DEVICE M68020 USER’S MANUAL S0 S2 PROCESSOR MOTOROLA ...
Page 120
... GT STATE1 X STATE 2 R R—BUS REQUEST G—BUS GRANT T —THREE-STATE CONTROL TO BUS CONTROL LOGIC X—DON'T CARE Figure 5-48. MC68EC020 Bus Arbitration State Diagram MOTOROLA STATE STATE STATE 6 R M68020 USER’ ...
Page 121
... For the duration of this sequence, the MC68EC020 ignores the BR input. If mastership of the MC68EC020 bus is required during a read-modify-write operation, BERR must be used to abort the read-modify-write sequence. The bus arbitration sequence while the bus is inactive (i.e., executing internal operations such as a multiply instruction) is shown in Figure 5-49. 5-74 M68020 USER’S MANUAL MOTOROLA ...
Page 122
... The speed of the AND gate must be faster than the time between the assertion of BGACK and the negation the alternate bus master. Figure 5-50 assumes the alternate bus master does not assume bus mastership until the MC68EC020 AS is negated and MC68EC020 BG is asserted. MOTOROLA BUS INACTIVE ALTERNATE MASTER INACTIVE OR HALTED) M68020 USER’ ...
Page 123
... Asserting RESET for 10 clock periods is sufficient for resetting the processor logic; the additional clock periods prevent a RESET instruction from overlapping the external RESET signal. 5-76 ALTERNATE BUS MASTER BGACK CC M68020 USER’S MANUAL MC68EC020 and clock timing have CC , and bus signals. The CC reaches the minimum operating MOTOROLA ...
Page 124
... RESET instruction must extend beyond the reset period of the instruction by at least eight clock cycles to reset the processor. Figure 5-52 shows the timing information for the RESET instruction. MOTOROLA t 520 CLOCKS t < 4 CLOCKS ENTIRE BUS ...
Page 125
... SIZ1–SIZ0 R/W ** ECS ** OCS AS DS DSACK1 DSACK0 ** DBEN D31–D0 HALT RESET READ For the MC68EC020, A23–A0. * This signal does not apply to the MC68EC020. ** Figure 5-52. RESET Instruction Timing 5-78 RESET INTERNAL 512 CLOCKS M68020 USER’S MANUAL S0 S2 RESUME NORMAL OPERATION MOTOROLA ...
Page 126
... For all other exceptions, internal logic provides the vector number. This vector number is used in the last step to calculate the address of the exception vector. Throughout this section, vector numbers are given in decimal notation. MOTOROLA M68020 USER’S MANUAL 6- 1 ...
Page 127
... MC68020/EC020. As shown in Table 6-1, the first 64 vectors are defined by Motorola, and 192 vectors are reserved for interrupt vectors defined by the user. However, external devices may use vectors reserved for internal purposes at the discretion of the system designer. ...
Page 128
... SP—Supervisor Program Space SD—Supervisor Data Space MOTOROLA Vector Offset Hex Space 000 SP Reset Initial Interrupt Stack Pointer 004 SP Reset Initial Program Counter 008 SD Bus Error 00C SD Address Error 010 SD Illegal Instruction ...
Page 129
... A bus error exception occurs when external logic aborts a bus cycle by asserting the BERR signal. If the aborted bus cycle is a data access, the processor immediately begins exception processing. If the aborted bus cycle is an instruction prefetch, the processor may delay taking the exception until it attempts to use the prefetched information. 6-4 M68020 USER’S MANUAL MOTOROLA ...
Page 130
... SR on the active supervisor stack. The saved PC value is the logical address of the instruction that was executing at the time the fault was detected. This is not necessarily the instruction that initiated the bus cycle since the processor overlaps MOTOROLA ENTRY S (SR) ...
Page 131
... RTE instruction from the trap handler is executed, and the trace corresponds to the trap instruction; the trap handler routine is not traced. The processor generates a vector number according to the instruction being executed; for the TRAP 6-6 M68020 USER’S MANUAL MOTOROLA ...
Page 132
... BERR , the instruction takes an unimplemented instruction (F-line opcode) exception. The system can emulate the functions of the coprocessor with an F-line exception handler. Refer to Section 7 Coprocessor Interface Description for more details. MOTOROLA 000 are used for coprocessor M68020 USER’S MANUAL 6- 7 ...
Page 133
... The saved value of the PC is the logical address of the first word of the instruction that caused the privilege violation. Instruction execution resumes after the required prefetches from the address in the privilege violation exception vector. 6-8 M68020 USER’S MANUAL MOTOROLA ...
Page 134
... This is of particular importance to an instruction emulation routine that performs the instruction function, adjusts the stacked PC to skip the unimplemented instruction, and returns. Before returning, the T1 and T0 bits of the SR on the stack should be checked. If MOTOROLA Table 6-2. Tracing Control Tracing Function No Tracing Trace on Change of Flow (BRA, JMP, etc ...
Page 135
... This exception saves a short bus fault stack frame, generates exception vector number 14, and continues execution at the address in the format exception vector. The stacked PC value is the logical address of the instruction that detected the format error. 6-10 M68020 USER’S MANUAL MOTOROLA ...
Page 136
... Table 6-3 lists the interrupt levels, the states of IPL2 – IPL0 that define each level, and the mask value that allows an interrupt at each level. MOTOROLA M68020 USER’S MANUAL 6- 11 ...
Page 137
... INTERRUPT PENDING * (MC68020 ASSERTS IPEND ) Control Line Status IPL2 IPL1 IPL0 Required for Recognition M68020 USER’S MANUAL Interrupt Mask Value * N/A 0 1–0 2–0 3–0 4–0 5–0 7–0 MOTOROLA ...
Page 138
... MOTOROLA M68020 USER’S MANUAL 6- 13 ...
Page 139
... AND AND STILL 111 ($7) THEN AND STILL 111 ($7) THEN 101 ($5) AND RTE SO THAT THEN M68020 USER’S MANUAL ACTION (LEVEL COMPARISON) LEVEL 6 INTERRUPT NO ACTION NO ACTION LEVEL 6 INTERRUPT (LEVEL COMPARISON) (TRANSITION) LEVEL 7 INTERRUPT NO ACTION (TRANSITION) NO ACTION LEVEL 7 INTERRUPT (LEVEL COMPARISON) MOTOROLA ...
Page 140
... Figure 6 flowchart of the interrupt recognition and associated exception processing sequence. CLK IPL2–IPL0 IPEND IPL2–IPL0 RECOGNIZED IPL2–IPL0 SYNCHRONIZED COMPARE REQUEST Figure 6-4. Assertion of IPEND (MC68020 Only) MOTOROLA ASSERT IPEND WITH MASK IN SR M68020 USER’S MANUAL 6- 15 ...
Page 141
... TEMP – (SP) PC – (SP) FORMAT WORD – (SP) OTHER EXCEPTION DEPENDENT INFORMATION VECTOR TABLE ENTRY PREFETCH 3 WORDS END OF EXCEPTION PROCESSING FOR THE INTERRUPT M68020 USER’S MANUAL TEMP BEGIN EXECUTION OF THE INTERRUPT HANDLER ROUTINE OR PROCESS A HIGHER PRIORITY EXCEPTION MOTOROLA ...
Page 142
... Most M68000 family peripherals use programmable interrupt vector numbers as part of the interrupt request/acknowledge mechanism of the system. If this vector number is not initialized after reset and the peripheral must acknowledge an interrupt request, the peripheral usually returns the uninitialized interrupt vector number (15). MOTOROLA M68020 USER’S MANUAL 6- 17 ...
Page 143
... However, most exceptions cannot occur during exception processing, and very few combinations of the exceptions shown in Table 6-4 can be pending simultaneously. 6-18 M68020 USER’S MANUAL MOTOROLA ...
Page 144
... Divide by Zero, RTE, RTM, TRAP, TRAPcc, TRAPV 3 3.0—Illegal Instruction, Line A, Unimplemented Line F, Privilege Violation, cp Preinstruction 4 4.0—cp Postinstruction 4.1—Trace 4.2—Interrupt NOTE: 0.0 is the highest priority; 4.2 is the lowest. MOTOROLA ENTRY A19–A16 $0 A4–A2 BREAKPOINT NUMBER INITIATE READ BUS CYCLE CYCLE TERMINATED WITH CYCLE TERMINATED WITH DSACK1/DSACK0 Aborts all processing (instruction or exception) and does not save old context ...
Page 145
... For the six-word stack frame, the processor restores the SR and PC values from the stack, increments the active supervisor stack pointer by 12, and resumes normal instruction execution. 6-20 M68020 USER’S MANUAL MOTOROLA ...
Page 146
... Otherwise, the processor reads the entire frame into the proper internal registers, deallocates the stack, and resumes normal processing. Once the processor begins to load the frame to restore its internal state, the assertion of the BERR signal MOTOROLA ENTRY TEMP (SP) + ...
Page 147
... The least significant half of the SSW applies to data cycles only. Data and instruction stream faults may be pending simultaneously; the fault handler should be able to recognize any combination of the FC, FB, RC, RB, and DF bits. 6-22 M68020 USER’S MANUAL MOTOROLA ...
Page 148
... FB bits are set, the RTE instruction automatically reruns the prefetch cycle for stage B. The address space for the bus cycle is the program space for the privilege level indicated in the copy of the SR on the stack. If the RB bit is clear, the words on the MOTOROLA 11 10 ...
Page 149
... B, if necessary Rerun faulted bus cycle or run pending prefetch not rerun bus cycle Bits 11–9—Reserved by Motorola DF—Fault/Rerun Flag If the DF bit is set, a data fault has occurred and caused the exception. If the DF bit is set when the processor reads the stack frame, it reruns the faulted data access; ...
Page 150
... RC) was not cleared by the software, the RTE reruns the associated instruction prefetch. The fault occurs again unless the cause of the fault, such as a nonresident page in a virtual memory system, has been corrected. If the bit is set and the MOTOROLA M68020 USER’S MANUAL 6- 25 ...
Page 151
... The system software should not depend on a particular exception generating a particular stack frame. For compatibility with future devices, the software should be able to handle any type of stack frame for any type of exception. Table 6-5 summarizes the stack frames defined for the MC68020/EC020. 6-26 M68020 USER’S MANUAL MOTOROLA ...
Page 152
... STATUS REGISTER +$02 PROGRAM COUNTER +$ VECTOR OFFSET +$08 INSTRUCTION ADDRESS +$0C INTERNAL REGISTERS, 4 WORDS +$12 COPROCESSOR MIDINSTRUCTION STACK FRAME (10 WORDS) — FORMAT $9 MOTOROLA Exception Types (Stacked PC Points to) 0 Interrupt Format Error TRAP #N Illegal Instruction A-Line Instruction F-Line Instruction Privilege Violation Coprocessor Preinstruction 0 Created on ...
Page 153
... Address Error or Bus Error — Execution Unit at Instruction Boundary 0 Address Error or Bus Error — Instruction Execution in Progress M68020 USER’S MANUAL [Next instruction] [Address of instruction in execution when fault occurred — may not be the instruction that generated the faulted bus cycle] MOTOROLA ...
Page 154
... This section is intended for designers who are implementing coprocessors to interface with the MC68020/EC020. The designer of a system that uses one or more Motorola coprocessors (the MC68881 or MC68882 floating-point coprocessor, for example) does not require a detailed knowledge of the M68000 coprocessor interface. Motorola coprocessors conform to the interface described in this section ...
Page 155
... The programming model for the M68000 family of microprocessors is based on sequential, nonconcurrent instruction execution, which implies that the instructions in a given sequence must appear to be executed in the order in which they occur. To maintain a uniform programming model, any coprocessor extensions should also maintain the 7-2 M68020 USER’S MANUAL MOTOROLA ...
Page 156
... The MC68020/EC020 uses the CpID field to indicate the coprocessor to which the instruction applies. F-line operation words, in which the CpID is zero, are not coprocessor instructions for the MC68020/EC020. Instructions with a CpID of zero and a nonzero type field are unimplemented instructions that cause the MOTOROLA ...
Page 157
... CpID equal to zero (except via the MOVES instruction). CpID codes of 000–101 are reserved for current and future Motorola coprocessors, and CpID codes of 110–111 are reserved for user-defined coprocessors. The Motorola CpID code of 001 designates the MC68881 or MC68882 floating-point coprocessor. By default, Motorola assemblers will use a CpID code of 001 when generating the instruction operation codes for the MC68881 or MC68882 ...
Page 158
... The MC68020/EC020 accesses the registers in the CIR set using standard asynchronous bus cycles. Thus, the bus interface implemented by a coprocessor for its interface register set must satisfy the MC68020/EC020 address, data, and control signal timing. The MC68020/EC020 bus operation is described in detail in Section 5 Bus Operation. MOTOROLA FC2–FC0 COPROCESSOR DECODE ...
Page 159
... M68000 coprocessor interface is shown in Figure 7-5. The individual registers are described in detail in 7.3 Coprocessor Interface Register Set. 7-6 ADDRESS BUS CpID CPU SPACE TYPE FIELD M68020 USER’S MANUAL CIR MOTOROLA 0 ...
Page 160
... M68000 coprocessor interface to request services from and indicate status to the main processor. During the execution of the instructions in the context save and context MOTOROLA INTERFACE REGISTER SET RESERVED INTERFACE REGISTER SET ...
Page 161
... An instruction in the coprocessor general instruction category optionally includes a number of extension words following the coprocessor command word. These words can provide additional information required for the coprocessor instruction. For example CpID COPROCESSOR COMMAND M68020 USER’S MANUAL 5 0 EFFECTIVE ADDRESS MOTOROLA ...
Page 162
... CIR and by reading the response CIR to determine its next action. The execution of the coprocessor instruction is then defined by the internal operation of the coprocessor and by its use of response primitives to request services from the main processor. This instruction protocol allows a wide range of operations to be implemented in the general instruction category. MOTOROLA M68020 USER’S MANUAL 7- 9 ...
Page 163
... RESPONSE CIR 7.4.1 ScanPC. for General Category Instructions M68020 USER’S MANUAL COPROCESSOR DECODE COMMAND WORD AND INITIATE WHILE (MAIN PROCESSOR SERVICE IS REQUIRED) RESPONSE PRIMITIVE CODE IN RESPONSE CIR REFLECT "NO COME AGAIN" IN RESPONSE CIR COMPLETE COMMAND EXECUTION REFLECT "PROCESSING FINISHED" STATUS IN MOTOROLA ...
Page 164
... Again" when used during the execution of a conditional category instruction "Come Again" attribute is not indicated in one of these primitives, the main processor will initiate protocol violation exception processing (see 7.5.2.1 Protocol Violations). Figure 7-8. Coprocessor Interface Protocol for Conditional Category Instructions MOTOROLA C1 DECODE COMMAND WORD AND INITIATE COMMAND EXECUTION C2 ...
Page 165
... CIR to transfer the condition selector to the coprocessor. The main 7- CpID OPTIONAL COPROCESSOR-DEFINED EXTENSION WORDS DISPLACEMENT Instruction Format (cpBcc. CpID OPTIONAL COPROCESSOR-DEFINED EXTENSION WORDS DISPLACEMENT — HIGH DISPLACEMENT — LOW Instruction Format (cpBcc.L) M68020 USER’S MANUAL 5 0 CONDITION SELECTOR 5 0 CONDITION SELECTOR MOTOROLA ...
Page 166
... CIR to determine its next action. The coprocessor can MOTOROLA M68020 USER’S MANUAL 7- 13 ...
Page 167
... M68000PM/AD, M68000 Family Programmer’s Reference Manual ). The second word of the cpScc instruction format contains the coprocessor condition selector field in bits 5–0. Bits 15–6 of this word are reserved by Motorola and should be zero to ensure compatibility with future M68000 products. This word is written to the condition CIR to initiate execution of the cpScc instruction ...
Page 168
... The second word of the cpDBcc instruction format contains the coprocessor condition selector field in bits 5–0 and should contain zeros in bits 15–6 (reserved by Motorola) to maintain compatibility with future M68000 products. This word is written to the condition CIR to initiate execution of the cpDBcc instruction. ...
Page 169
... F-line operation word specify the opmode, which selects the instruction format. The instruction format can include zero, one, or two operand words. 7- CpID (RESERVED) OPTIONAL COPROCESSOR-DEFINED EXTENSION WORDS OPTIONAL WORD OR LONG-WORD OPERAND Instruction Format (cpTRAPcc) M68020 USER’S MANUAL OPMODE CONDITION SELECTOR MOTOROLA ...
Page 170
... The second word of the cpTRAPcc instruction format contains the coprocessor condition selector in bits 5–0 and should contain zeros in bits 15–6 (these bits are reserved by Motorola) to maintain compatibility with future M68000 products. This word is written to the condition CIR to initiate execution of the cpTRAPcc instruction. ...
Page 171
... The number of entries following the format word (at higher addresses) is determined by the format word length for a given coprocessor state. 7- LENGTH COPROCESSOR-DEPENDENT INFORMATION M68020 USER’S MANUAL 0 (UNUSED, RESERVED) MOTOROLA ...
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... If the main processor reads the empty/reset format word from the save CIR during the initiation of a cpSAVE instruction, it stores the format word at the effective address specified in the cpSAVE instruction and executes the next instruction. MOTOROLA Length Meaning $xx ...
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... In this situation, the coprocessor can return the invalid format word when the main processor reads the save CIR to initiate the cpSAVE instruction while either another cpSAVE or cpRESTORE instruction is executing. If the 7-20 M68020 USER’S MANUAL MOTOROLA ...
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... F-Line Emulator Exceptions. The instruction can include as many as five effective address extension words following the F-line operation word. These words contain any additional information required to calculate the effective address specified by bits 5–0 of the F-line operation word. MOTOROLA ...
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... MC68020/EC020 initiates format error exception processing (refer to 7.5.1.5 Format Errors). The coprocessor and main processor coordinate the transfer of the internal state of the coprocessor using the operand CIR. The MC68020/EC020 completes the coprocessor context save by repeatedly reading the operand CIR and writing the 7-22 M68020 USER’S MANUAL COPROCESSOR MOTOROLA ...
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... M68000 effective addressing code in bits 5–0. The effective address encoded in the cpRESTORE instruction is the starting address in memory where the coprocessor context is stored. The effective address is that of the coprocessor format word that applies to the context to be restored to the coprocessor. MOTOROLA ...
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... CIR. 7-24 C1 TERMINATE CURRENT OPERATIONS AND EVALUATE FORMAT WORD C2 IF (INVALID FORMAT) PLACE INVALID FORMAT CODE IN THE RESTORE CIR C3 IF (VALID FORMAT) RECEIVE NUMBER OF BYTES INDICATED IN FORMAT WORD THROUGH OPERAND CIR M68020 USER’S MANUAL COPROCESSOR MOTOROLA ...
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... CIR set for the control CIR is $02. The control CIR occupies the two least significant bits of the word at that offset. The 14 most significant bits of the word are undefined and reserved by Motorola. Figure 7-19 shows the format of this register. ...
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... F-line operation word in the instruction stream, to the 16-bit command CIR. The offset from the base address of the CIR set for the command CIR is $0A. 7-26 (UNDEFINED, RESERVED) Figure 7-19. Control CIR Format M68020 USER’S MANUAL MOTOROLA ...
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... The main processor initiates a conditional category instruction by writing the condition selector to bits 5–0 of the 16-bit condition CIR. Bits 15–6 are undefined and reserved by Motorola. The offset from the base address of the CIR set for the condition CIR is $0E. Figure 7-20 shows the format of the condition CIR. ...
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... MC68020/EC020 does not recognize causes it to initiate protocol violation exception processing (refer to 7.5.2.1 Protocol Violations). This processing of undefined primitives supports emulation of extensions to the M68000 coprocessor response primitive set by the protocol violation exception handler. Exception processing related to the coprocessor interface is discussed in 7.5 Exceptions. 7-28 M68020 USER’S MANUAL MOTOROLA ...
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... The M68000 coprocessor response primitives are encoded in a 16-bit word that is transferred to the main processor through the response CIR. Figure 7-22 shows the format of the coprocessor response primitives Figure 7-22. Coprocessor Response Primitive Format MOTOROLA 8 7 FUNCTION M68020 USER’S MANUAL 0 PARAMETER 7- 29 ...
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... If the DR bit is set, the direction of transfer is from the coprocessor to the main processor (main processor read). If the operation indicated by a given response primitive does not involve an explicit operand transfer, the value of this bit depends on the particular primitive encoding. 7-30 M68020 USER’S MANUAL MOTOROLA ...
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... A design that uses a breakpoint to monitor the number of passes through a loop by incrementing or decrementing a counter may not work correctly under these conditions. This special case may cause several breakpoint acknowledge cycles to be executed during a single pass through a loop. MOTOROLA ...
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... from the response CIR (refer to 7.5.2.5 Trace Exceptions). Thus, the main processor continues to read the response CIR until it receives a null primitive with 7- Figure 7-24. Null Primitive Format M68020 USER’S MANUAL MOTOROLA ...
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... Coprocessor Instruction Completed; Service Pending Exceptions or Execute Next Instruction x = Don't Care Depending on Coprocessor Condition Evaluation MOTOROLA General Instructions M68020 USER’S MANUAL Conditional Instructions Same as General Category Same as General Category Same as General Category Main Processor Completes Instruction Execution Based ...
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... Figure 7-26 shows the format of the transfer operation word primitive Figure 7-26. Transfer Operation Word Primitive Format 7- M68020 USER’S MANUAL MOTOROLA ...
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... The main processor transfers the operands from the instruction stream, using a sequence of long-word writes, to the operand CIR. If the length field is not an even multiple of four bytes, the last two bytes from the instruction stream are transferred using a word write to the operand CIR. MOTOROLA ...
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... Figure 7-29. Evaluate Effective Address and This primitive uses the CA, PC, and DR bits as described in 7.4.2 Coprocessor Response Primitive General Format. 7- VALID EA Transfer Data Primitive Format M68020 USER’S MANUAL LENGTH MOTOROLA ...
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... Using long-word transfers whenever possible, the main processor then transfers the number of bytes specified in the primitive between the operand CIR and the effective address. Refer to 7.3.8 Operand CIR for information concerning operand alignment for transfers involving the operand CIR. MOTOROLA Category Control Alterable Data Alterable ...
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... Figure 7-30 shows the format of the write to previously evaluated effective address primitive Figure 7-30. Write to Previously Evaluated Effective Address Primitive Format 7- M68020 USER’S MANUAL 0 LENGTH MOTOROLA ...
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... That is, this primitive uses the value from an evaluate and transfer effective address, evaluate effective address and transfer data, or transfer multiple coprocessor registers primitive without modification. MOTOROLA M68020 USER’S MANUAL 7- 39 ...
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... The function code used with the address read from the operand address CIR indicates either supervisor or user data space according to the value of the S-bit in the MC68020/EC020 SR. 7- M68020 USER’S MANUAL 0 LENGTH MOTOROLA ...
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... Figure 7-33. Transfer Single Main Processor Register Primitive Format The transfer single main processor register primitive uses the CA, PC, and DR bits as described in 7.4.2 Coprocessor Response Primitive General Format. If the coprocessor issues this primitive with during a conditional category instruction, the main processor initiates protocol violation exception processing. MOTOROLA ...
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... Table 7-5. Main Processor Control Register Select Codes Control Register $x000 SFC $x001 DFC $x002 CACR $x800 USP $x801 VBR $x802 CAAR $x803 MSP $x804 ISP M68020 USER’S MANUAL MOTOROLA ...
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... This primitive applies to general category instructions. If the coprocessor issues this primitive during the execution of a conditional category instruction, the main processor initiates protocol violation exception processing. Figure 7-37 shows the format of the transfer multiple coprocessor registers primitive. MOTOROLA ...
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... The address register used with the (An)+ addressing mode is incremented by the total number of bytes transferred during the primitive execution. 7- M68020 USER’S MANUAL 0 LENGTH MOTOROLA ...
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... The transfer status register and scanPC primitive uses the CA, PC, and DR bits as described in 7.4.2 Coprocessor Response Primitive General Format. The SP bit selects the scanPC option the primitive transfers both the scanPC and SR only the SR is transferred. MOTOROLA ...
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... When the main processor receives this primitive, it acknowledges the coprocessor exception request by writing an exception acknowledge mask to the control CIR (refer to 7.3.2 Control CIR). The MC68020/EC020 then proceeds with exception processing as 7- M68020 USER’S MANUAL 0 VECTOR NUMBER MOTOROLA ...
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... The coprocessor should record the addresses of all general category instructions that can be executed concurrently with the main processor and that support exception recovery. Since the exception is not reported until the next coprocessor instruction is initiated, the processor usually requires the instruction address to determine MOTOROLA 12 11 STATUS REGISTER ...