MC68HC11KA1CFN4 Motorola, MC68HC11KA1CFN4 Datasheet
MC68HC11KA1CFN4
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MC68HC11KA1CFN4 Summary of contents
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... Available in 68-Pin Plastic Leaded Chip Carrier (Custom ROM/OTPROM), 68-Pin Windowed Ce- ramic Leaded Chip Carrier (EPROM), or 64-Pin Quad Flat Pack (Custom ROM/OTPROM) This document contains information on a new product. Specifications and information herein are subject to change without notice. © MOTOROLA INC., 1996 Order this document by MC68HC11KA4TS/D ...
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... Kbytes OTPROM $DF 24 Kbytes OTPROM $DF 32 Kbytes OTPROM $DF 32 Kbytes OTPROM $DF 32 Kbytes OTPROM Frequency MC Order Number 4 MHz MC68HC11KA4BCFN4 2 MHz MC68HC11KA1CFN2 3 MHz MC68HC11KA1CFN3 4 MHz MC68HC11KA1CFN4 2 MHz MC68HC11KA1VFN2 3 MHz MC68HC11KA1VFN3 4 MHz MC68HC11KA1VFN4 2 MHz MC68HC11KA1MFN2 3 MHz MC68HC11KA1MFN3 4 MHz MC68HC11KA1MFN4 2 MHz MC68HC11KA0CFN2 3 MHz MC68HC11KA0CFN3 4 MHz ...
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... MHz MC68HC711KA2CFU3 4 MHz MC68HC711KA2CFU4 2 MHz MC68HC711KA2VFU2 3 MHz MC68HC711KA2VFU3 4 MHz MC68HC711KA2VFU4 2 MHz MC68HC711KA2MFU2 3 MHz MC68HC711KA2MFU3 4 MHz MC68HC711KA2MFU4 2 MHz MC68HC11KA1CFU2 3 MHz MC68HC11KA1CFU3 4 MHz MC68HC11KA1CFU4 2 MHz MC68HC11KA1VFU2 3 MHz MC68HC11KA1VFU3 4 MHz MC68HC11KA1VFU4 2 MHz MC68HC11KA0CFU2 3 MHz MC68HC11KA0CFU3 4 MHz MC68HC11KA0CFU4 2 MHz MC68HC11KA0VFU2 3 MHz MC68HC11KA0VFU3 4 MHz MC68HC11KA0VFU4 MOTOROLA 3 ...
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... Table 1 Standard Device Ordering Information (Continued) Package Temperature 68-Pin Cerquad – – 105 C – 125 C – – 105 C – 125 C MOTOROLA 4 CONFIG Description $DF 24 Kbytes EPROM $DF 24 Kbytes EPROM $DF 24 Kbytes EPROM $DF 32 Kbytes EPROM $DF 32 Kbytes EPROM $DF 32 Kbytes EPROM ...
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... MHz No EEPROM 3 MHz 4 MHz 24 Kbytes Custom ROM, 2 MHz No EEPROM 3 MHz 4 MHz MC Order Number MC68HC11KA4CFN2 MC68HC11KA4CFN3 MC68HC11KA4CFN4 MC68HC11KA4VFN2 MC68HC11KA4VFN3 MC68HC11KA4VFN4 MC68HC11KA4MFN2 MC68HC11KA4MFN3 MC68HC11KA4MFN4 MC68HC11KA2CFN2 MC68HC11KA2CFN3 MC68HC11KA2CFN4 MC68HC11KA2VFN2 MC68HC11KA2VFN3 MC68HC11KA2VFN4 MC68HC11KA2MFN2 MC68HC11KA2MFN3 MC68HC11KA2MFN4 MC68HC11KA3CFN2 MC68HC11KA3CFN3 MC68HC11KA3CFN4 MC68HC11KA3VFN2 MC68HC11KA3VFN3 MC68HC11KA3VFN4 MC68HC11KA3MFN2 MC68HC11KA3MFN3 MC68HC11KA3MFN4 MOTOROLA 5 ...
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... C – 105 C Table 3 Extended Voltage (3.0 Vdc to 5.5 Vdc) Device Ordering Information Package Temperature 68-Pin Plastic – Leaded Chip Carrier 64-Pin Quad – Flat Pack MOTOROLA 6 Description Frequency 24 Kbytes Custom ROM 2 MHz 3 MHz 4 MHz 24 Kbytes Custom ROM 2 MHz 3 MHz 4 MHz ...
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... Figure 1 Pin Assignments for 68-Pin Plastic Leaded Chip Carrier/Cerquad MC68HC11KA4 MC68HC11KA4TS MC68HC(7)11KA4 52 MC68HC(7)11KA2 MODA/LIR MODB/V STBY RESET XTAL EXTAL XOUT E PC7/DATA7 PC6/DATA6 PC5/DATA5 PC4/DATA4 PC3/DATA3 PC2/DATA2 PC1/DATA1 PC0/DATA0 PF0/ADDR0 PF1/ADDR1 MOTOROLA 7 ...
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... PA7/PAI/OC1 9 PA6/OC2/OC1 10 PA5/OC3/OC1 11 PA4/OC4/OC1 12 PA3/OC5/IC4/OC1 13 PA2/IC1 14 PA1/IC2 15 PA0/IC3 PPE applies to MC68HC711KA4 and MC68HC711KA2 only. Figure 2 Pin Assignments for 64-Pin Quad Flat Pack MOTOROLA MC68HC(7)11KA4 41 MC68HC(7)11KA2 PF1/ADDR1 PF2/ADDR2 PF3/ADDR3 ...
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... AN2 PE2 AN1 PE1 AN0 PE0 INTERNAL V SS A/D CONVERTER V DD EXTERNAL V SS PWM PW4 PH3 PW3 PH2 PW2 PH1 PW1 PH0 SS PD5 SCK PD4 SPI MOSI PD3 MISO PD2 PD1 TxD PD0 RxD SCI PG7 MOTOROLA 9 1 ...
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... Electrically Erasable Programmable Read-Only Memory 5 Resets and Interrupts 6 Parallel Input/Output 7 Serial Communications Interface 8 Serial Peripheral Interface 9 Analog-to-Digital Converter 10 Main Timer 10.1 Real-Time Interrupt ...................................................................................................................58 11 Pulse Accumulator 12 Pulse-Width Modulation Timer MOTOROLA 10 TABLE OF CONTENTS Page MC68HC11KA4 MC68HC11KA4TS/D ...
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... ROM/EPROM in the memory map. In special test mode, the ROMON bit is forced to zero so that the ROM/EPROM is removed from the memory map. In single-chip mode, the ROMAD bit is forced to one, causing the ROM/EPROM to be enabled at $A000–$FFFF ($8000–$FFFF in the MC68HC11KA2). This guarantees that there will be ROM/EPROM at the vector space. MC68HC11KA4 MC68HC11KA4TS/D MOTOROLA 11 ...
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... EPROM can be enabled in special test mode by setting the ROMON bit in the config register after reset. 2. 768 bytes RAM in MC68HC711KA4, 1024 bytes RAM in MC68HC711KA2 Kbytes ROM/EPROM in MC68HC711KA4, 32 Kbytes ROM/EPROM in MC68HC711KA2. Figure 4 Memory Map for MC68HC11KA4 MOTOROLA 12 128-BYTE REGISTER BLOCK 0000 (CAN BE REMAPPED TO ANY ...
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... PAGE BY THE INIT2 REGISTER) 0FFF 8000 32 KBYTES ROM/EPROM (NOTE 3) (CAN BE REMAPPED TO $0000–$7FFF OR $8000–$FFFF BY THE CONFIG REGISTER) FFFF SPECIAL TEST BOOT ROM BE00 (ONLY PRESENT IN BOOTSTRAP MODE) SPECIAL MODE BFC0 INTERRUPT BFFF VECTORS FFC0 NORMAL MODE INTERRUPT FFFF VECTORS MOTOROLA 13 ...
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... REGISTER BLOCK (128 BYTES) $007F $0080 RAM B (896 BYTES) $03FF $0400 RAM A (128 BYTES) $047F Figure 7 RAM and Register Mapping for MC68HC11KA2 MOTOROLA 14 INIT = $10 INIT = $04 REG @ $0000 REG @ $4000 RAM @ $1000 RAM @ $0000 $0000 $0000 REGISTER RAM BLOCK A (128 BYTES) (128 BYTES) ...
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... Bit 0 TOC4 (Low) 9 Bit 8 TI4/O5 (High) 1 Bit 0 TI4/O5 (Low) OM5 OL5 TCTL1 EDG3B EDG3A TCTL2 IC2I IC3I TMSK1 IC2F IC3F TFLG1 PR1 PR0 TMSK2 0 0 TFLG2 RTR1 RTR0 PACTL 1 Bit 0 PACNT SPR1 SPR0 SPCR 0 0 SPSR 1 Bit 0 SPDR 0 EPGM EPROG MOTOROLA 15 ...
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... Bit 7 6 $0070 BTST BSPL $0071 SBR7 SBR6 SBR5 $0072 LOOPS WOMS $0073 TIE TCIE $0074 TDRE TC RDRF $0075 0 0 MOTOROLA HPPUE GPPUE — — — — — — — — — — — — MULT CD CC ...
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... Bit SCDRH R1/T1 R0/T0 SCDRL — — Reserved — — Reserved PH1 PH0 PORTH DDH1 DDH0 DDRH 0 0 PORTG 0 0 DDRG $003C 1 Bit Single Chip 1 0 Expanded 1 0 Bootstrap 1 0 Special Test Latched at Reset SMOD MDA MOTOROLA 17 ...
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... PAREN — Pull-Up Assignment Register Enable Refer to 6 Parallel Input/Output. NOSEC — Security Disable NOSEC is invalid unless the security mask option is specified before the MCU is manufactured. If se- curity mask option is omitted NOSEC always reads one Security enabled 1 = Security disabled MOTOROLA RAM1 RAM0 ...
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... Refer to 8 Serial Peripheral Interface. MC68HC11KA4 MC68HC11KA4TS — IRVNE LSBF SPR2 0 — Clock Out of IRV Out of Reset Reset On Off On Off On Off On On $0038 1 Bit 0 XDV1 XDV0 0 0 IRVNE IRVNE Affects Only Can Be Written E Once IRV Once E Once IRV Once MOTOROLA 19 ...
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... XDV[1:0] EXTAL Divided The XOUT pin is not bonded in the 64-pin package. MOTOROLA 20 Table 5 XOUT Frequencies Frequency at Frequency at EXTAL = 8 MHz EXTAL = 12 MHz 8 MHz 12 MHz 2 MHz 3 MHz 1.33 MHz 2 MHz 1 MHz 1.5 MHz Frequency at Frequency at EXTAL = 8.4 MHz EXTAL = 12.6 MHz 8 ...
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... EXROW — Select Extra Row Used for factory test purposes only Bits [2:1] — Not implemented Always read zero MC68HC11KA4 MC68HC11KA4TS/D voltage. PPE ELAT EXCOL EXROW — There are two meth- PPE $002B 1 Bit 0 — EPGM 0 0 MOTOROLA 21 ...
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... Unused Inputs – these pins may be left unterminated. 3. Unused Outputs – these pins should be left unconnected. 4. Grounding these six pins configures the MC68HC711KA4/KA2 for EPROM emulation mode. Figure 8 Wiring Diagram for MC68HC711KA4/KA2 EPROM in PROG Mode MOTOROLA 22 EPROM MODE PIN CONNECTIONS MCU PIN FUNCTIONS ...
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... EEPROM is electronically removed from the memory map; thus not accessible during the program/erase cycle. Care must be taken to ensure that EEPROM resources will not be needed by any routines in the code during the 10 ms program/erase time. MC68HC11KA4 MC68HC11KA4TS/D CAUTION MOTOROLA 23 ...
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... INIT2 can be written only once in normal modes, any time in special modes. EE[3:0] — EEPROM Map Position EEPROM is at $xD80–$xFFF, where x is the hexadecimal digit represented by EE[3:0] bits. Bits [3:0] — Not implemented Always read zero MOTOROLA BPRT4 PTCON BPRT3 ...
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... LVPI BYTE ROW ERASE has fallen below a safe operating volt- DD returns to a safe operating voltage or if LVPEN bit in BPROT DD ROW Action 0 Bulk Erase (All 640 Bytes) 1 Row Erase (16 Bytes) 0 Byte Erase 1 Byte Erase $003B 1 Bit 0 EELAT EEPGM 0 0 MOTOROLA 25 ...
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... SCI status register to check for receive errors, then to read the received data from the SCI data register. These two steps satisfy the automatic clearing mechanism without re- quiring any special instructions. Refer to the following table for a list of interrupt and reset vector assignments MOTOROLA 26 MC68HC11KA4 MC68HC11KA4TS/D ...
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... Mask Bit — — I RIE RIE TIE TCIE ILIE I SPIE I PAII I PAOVI I TOI I I4/O5I I OC4I I OC3I I OC2I I OC1I I IC3I I IC2I I IC1I I RTII I None X None None None None None None NOCOP None CME None None $0039 2 1 Bit 0 CR1* CR0 MOTOROLA 27 ...
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... Refer to 2 Operating Modes and On-Chip Memory. SMOD — Special Mode Select Refer to 2 Operating Modes and On-Chip Memory. MDA — Mode Select A Refer to 2 Operating Modes and On-Chip Memory. MOTOROLA 28 Table 6 COP Timer Rate Select XTAL = 8.0 MHz XTAL = 12.0 MHz Time-out Time-out – ...
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... SPI Serial Transfer Complete 0 0 SCI Serial System 0 1 Reserved (Default to IRQ Reserved (Default to IRQ Reserved (Default to IRQ Reserved (Default to IRQ CLKX PAREN NOSEC NOCOP — — — $003F 2 1 Bit 0 ROMON EEON — — — MOTOROLA 29 ...
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... NOCOP — COP System Disable Resets to programmed value 0 = COP enabled (forces reset on time-out COP disabled (does not force reset on time-out) ROMON — ROM/EPROM Enable Refer to 2 Operating Modes and On-Chip Memory. EEON — EEPROM Enable Refer to 2 Operating Modes and On-Chip Memory. MOTOROLA 30 MC68HC11KA4 MC68HC11KA4TS/D ...
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... CLKX PAREN NOSEC NOCOP — — — Shared Functions Timer High Order Address Data Bus SCI and SPI A/D Converter Low Order Address R/W Signal PWMs $003F 2 1 Bit 0 ROMON EEON — — — MOTOROLA 31 ...
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... TI4/O5 register is acting as IC4. PA7 drives the pulse ac- cumulator input but also can be configured for general-purpose I/O, or output com- pare. Note that even when PA7 is configured as an output, the pin still drives the pulse accumulator input. MOTOROLA ...
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... PF4 PF3 PF2 ADDR5 ADDR4 ADDR3 ADDR2 $0001 2 1 Bit 0 DDA1 DDA0 $0004 2 1 Bit 0 PB1 PB0 PB1 PB0 ADDR9 ADDR8 $0002 2 1 Bit 0 DDB1 DDB0 $0005 2 1 Bit 0 PF1 PF0 PF1 PF0 ADDR1 ADDR0 MOTOROLA 33 ...
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... DDC[7:0] — Data Direction for Port Bits set to zero to configure corresponding I/O pin for input only 1 = Bits set to one to configure corresponding I/O pin for output PORTD — Port D Data Bit RESET Alt. Pin Func.: — — MOTOROLA DDF5 DDF4 DDF3 DDF2 ...
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... NOTE PE5* PE4* PE3 PE2 AN5 AN4 AN3 AN2 — — HPPUE GPPUE NOTE $0009 1 Bit 0 DDD1 DDD0 0 0 $000A 1 Bit 0 PE1 PE0 U U AN1 AN0 $002C 1 Bit 0 FPPUE BPPUE 1 1 MOTOROLA 35 ...
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... Bit set to zero to configure corresponding I/O pin for input only 1 = Bit set to one to configure corresponding I/O pin for output In expanded and test modes, bit 7 is configured for R/W, forcing the state of this pin output although the DDRG value remains zero. Bits [6:0] — Not implemented Always read zero MOTOROLA — ...
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... EXTAL OSCILLATOR AND CLOCK GENERATOR ( 4) XTAL Figure 9 SCI Baud Generator Circuit Diagram MC68HC11KA4 MC68HC11KA4TS/D INTERNAL BUS CLOCK (PH2) 3 0:0 0 SCR[2:0] 0:0:0 2 0:0:1 2 0:1:0 2 0:1:1 2 1:0:0 2 1:0:1 2 1:1:0 2 1:1 SCP[1:0] 1:0 1:1 16 SCI TRANSMIT BAUD RATE (1X) SCI RECEIVE BAUD RATE (16X) SCI BAUD GENERATOR MOTOROLA 37 ...
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... BAUD RATE CLOCK 10 (11) - BIT Tx SHIFT REGISTER H ( PARITY GENERATOR SCCR1 SCI CONTROL 1 SCI Rx SCI INTERRUPT REQUESTS REQUEST Figure 10 SCI Transmitter Block Diagram MOTOROLA 38 (WRITE-ONLY) L FORCE PIN DIRECTION (OUT) TRANSMITTER CONTROL LOGIC SCSR INTERRUPT STATUS TDRE TIE TC ...
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... Figure 11 SCI Receiver Block Diagram MC68HC11KA4 MC68HC11KA4TS/D 16 DATA ( RECOVERY RE PARITY DETECT M LOGIC SCSR1 SCI STATUS 1 RDRF RIE IDLE ILIE OR RIE SCCR2 SCI CONTROL 2 10 (11) - BIT Rx SHIFT REGISTER MSB ALL ONES RWU SCDR Rx BUFFER (READ-ONLY) INTERNAL DATA BUS MOTOROLA 39 ...
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... WOMS RESET LOOPS — SCI LOOP Mode Enable 0 = SCI transmit and receive operate normally 1 = SCI transmit and receive are disconnected from TxD and RxD pins, and transmitter output is fed back into the receiver input MOTOROLA — SBR12 SBR11 ...
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... SCI interrupt requested when RDRF flag or the OR status flag is set ILIE — Idle Line Interrupt Enable 0 = IDLE interrupts disabled 1 = SCI interrupt requested when IDLE status flag is set TE — Transmitter Enable 0 = Transmitter disabled 1 = Transmitter enabled MC68HC11KA4 MC68HC11KA4TS RIE ILIE $0073 1 Bit 0 RWU SBK 0 0 MOTOROLA 41 ...
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... OR flag by reading SCSR1 with OR set and then reading SCDR overrun 1 = Overrun detected NF — Noise Error Flag NF is set if majority sample logic detects anything other than a unanimous decision. Clear NF by reading SCSR1 with NF set and then reading SCDR Unanimous decision 1 = Noise detected MOTOROLA RDRF IDLE OR ...
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... Always read zero R/T[7:0] — Receiver/Transmitter Data Bits [7:0] SCI data is double buffered in both directions. MC68HC11KA4 MC68HC11KA4TS — — — — — — — R5/T5 R4/T4 R3/T3 R2/T2 $0075 2 1 Bit 0 — — RAF $0076, $0077 1 Bit 0 — — SCDRH (High) R1/T1 R0/T0 SCDRL (Low) MOTOROLA 43 ...
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... SPI baud rate clock divider. INTERNAL MCU CLOCK DIVIDER SPI CLOCK (MASTER) SELECT SPI CONTROL SPI STATUS REGISTER SPI INTERRUPT REQUEST MOTOROLA 44 MSB LSB 8/16-BIT SHIFT REGISTER READ DATA BUFFER CLOCK CLOCK LOGIC MSTR SPE 8 SPI CONTROL REGISTER 8 ...
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... SLAVE CPHA=1 TRANSFER IN PROGRESS MASTER TRANSFER IN PROGRESS SLAVE CPHA=0 TRANSFER IN PROGRESS Figure 13 SPI Transfer Format $0028 2 1 Bit 0 CPHA SPR1 SPR0 LSB 2 1 LSB 4 5 SPI TRANSFER FORMAT 1 MOTOROLA 45 ...
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... No mode fault 1 = Mode fault (SS is pulled low while MSTR = 1) Bits [3:0] — Not implemented Always read zero SPDR —SPI Data Bit 7 6 Bit 7 6 SPI is double buffered in, single buffered out. MOTOROLA 46 NOTE Divide Frequency at E Clock MHz (Baud) 2 1.0 MHz 4 500 kHz ...
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... SPR2 — SPI Clock (SCK) Rate Select Adds a divide by four prescaler to SPI clock chain. Refer to SPCR register. XDV[1:0] — XOUT Clock Divide Select Refer to 2 Operating Modes and On-Chip Memory. MC68HC11KA4 MC68HC11KA4TS — IRVNE LSBF SPR2 0 — $0038 1 Bit 0 XDV1 XDV0 0 0 MOTOROLA 47 ...
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... ADR1 A/D RESULT 1 Figure 14 A/D Converter Block Diagram The A/D converter can operate in single or multiple conversion modes. Multiple conversions are per- formed in sequences of four. Sequences can be performed on a single channel group of chan- nels. MOTOROLA 48 8-BIT CAPACITIVE DAC WITH SAMPLE AND HOLD SUCCESSIVE APPROXIMATION ...
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... CHANNEL, UPDATE ADR2 64 ADR3 96 DIFFUSION/POLY COUPLER + ~12V 4 K – ~0.7V 400 nA JUNCTION DUMMY N-CHANNEL LEAKAGE OUTPUT DEVICE and RH BIT 1 LSB CYC CYC CYC END CONVERT FOURTH CHANNEL, UPDATE ADR4 128 — E CYCLES A/D CONVERSION TIM * ~ 20 pF DAC CAPACITANCE V RL ANALOG INPUT PIN MOTOROLA 49 ...
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... ADR[4:1] —A/D Results $0031 Bit 7 6 $0032 Bit 7 6 $0033 Bit 7 6 $0034 Bit 7 6 MOTOROLA SCAN MULT Channel CB CA Signal 0 0 AN0 0 1 AN1 1 0 AN2 1 1 ...
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... Refer to 5 Resets and Interrupts. FCME — Force Clock Monitor Enable Refer to 5 Resets and Interrupts. CR[1:0] — COP Timer Rate Select Refer to 5 Resets and Interrupts. MC68HC11KA4 MC68HC11KA4TS IRQE* DLY* CME FCME $0039 1 Bit 0 CR1* CR0 MOTOROLA 51 ...
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... CR[1: 16.384 65.536 262. 1.049 s Time-out Tolerance (–0 ms/+...) 16.4 ms MOTOROLA 52 Table 9 Timer Summary XTAL Frequencies 12.0 MHz 16.0 MHz 3.0 MHz 4.0 MHz 333 ns 250 ns Main Timer Count Rates 333 ns 250 ns 21.845 ms 16.384 ms 1.333 s 1.0 s 87.381 ms 65 ...
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... INTERRUPT REQUESTS (FURTHER QUALIFIED BY I-BIT IN CCR) PIN FUNCTIONS 8 PA7/ OC1/ BIT-7 PAI 7 PA6/ OC2/ BIT-6 OC1 6 PA5/ OC3/ BIT-5 OC1 5 PA4/ OC4/ BIT-4 OC1 4 PA3 OC5/ BIT-3 IC4/ OC1 PA2/ 3 BIT-2 IC1 PA1/ 2 BIT-1 IC2 PA0/ 1 BIT-0 IC3 PORT A PIN CONTROL MOTOROLA 53 ...
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... TCNT resets to $0000. In normal modes, TCNT is read-only. TIC1–TIC3 —Timer Input Capture $0010 Bit 15 14 $0011 Bit 7 6 $0012 Bit 15 14 $0013 Bit 7 6 $0014 Bit 15 14 $0015 Bit 7 6 TICx not affected by reset MOTOROLA FOC3 FOC4 FOC5 OC1M5 OC1M4 OC1M3 ...
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... Bit 8 High TOC1 1 Bit 0 Low 9 Bit 8 High TOC2 1 Bit 0 Low 9 Bit 8 High TOC3 1 Bit 0 Low 9 Bit 8 High TOC4 1 Bit 0 Low $001E, $001F 9 Bit 8 High 1 Bit 0 Low $0020 2 1 Bit 0 OL4 OM5 OL5 $0021 2 1 Bit 0 EDG2A EDG3B EDG3A MOTOROLA 55 ...
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... RESET TOI — Timer Overflow Interrupt Enable 0 = Timer overflow interrupt disabled 1 = Timer overflow interrupt enabled RTII — Real-Time Interrupt Enable 0 = RTIF interrupts disabled 1 = Interrupt requested when RTIF is set to one. MOTOROLA 56 EDGxA Configuration 0 Capture disabled 1 Capture on rising edges only 0 Capture on falling edges only ...
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... PAIF — Pulse Accumulator Input Edge Flag Refer to 11 Pulse Accumulator. Bits [3:0] — Not implemented Always read zero MC68HC11KA4 MC68HC11KA4TS/D NOTE PR[1:0] Prescaler PAOVF PAIF — — $0025 1 Bit 0 — — MOTOROLA 57 ...
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... The RTR1 and RTR0 control bits select an additional division factor. RTI is set to its fastest rate by default out of reset and can be changed at any time. Refer to interrupt enable and flag bits in TMSK2 and TFLG2 registers. RTR [1:0] Divide MOTOROLA PAMOD PEDGE — ...
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... PAI EDGE PAEN 2:1 CLOCK MUX DATA BUS PAEN PACTL CONTROL INTERNAL DATA BUS 12.0 MHz 16.0 MHz 3.0 MHz 4.0 MHz 333 ns 250 ns 21.330 s 16.0 s 5.461 ms 4.096 ms PAOVI 1 PAOVF INTERRUPT REQUESTS PAII 2 PAIF TFLG2 INTERRUPT STATUS DISABLE FLAG SETTING OVERFLOW PACNT 8-BIT COUNTER ENABLE MOTOROLA 59 ...
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... PAOVF — Pulse Accumulator Overflow Flag Set when PACNT changes from $FF to $00 PAIF — Pulse Accumulator Input Edge Flag Set each time a selected active edge is detected on the PAI input line Bits [3:0] — Not implemented Always read zero MOTOROLA PAOVI PAII — ...
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... RTR[1:0] — Real-Time Interrupt Rate Refer to 10 Main Timer. PACNT —Pulse Accumulator Counter Bit 7 6 Bit 7 6 Can be read and written. MC68HC11KA4 MC68HC11KA4TS PAMOD PEDGE — I4/ $0026 2 1 Bit 0 RTR1 RTR0 $0027 2 1 Bit Bit 0 MOTOROLA 61 ...
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... MHz, PWM periods greater than one minute are possible. In 16-bit mode, duty cycle resolution of almost 15 parts per million can be achieved (at a PWM frequen about 60 Hz). In the same system, a PWM frequency of 1 kHz corresponds to a duty cycle reso- lution of 0.025%. MOTOROLA 62 MC68HC11KA4 MC68HC11KA4TS/D ...
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... PWDTY4 PWM OUTPUT PWDTY PWPER CLOCK S 2 CLOCK A PWEN1 CLOCK PWEN2 SELECT CON12 CNT1 CNT2 PPOL1 Q PH0/ MUX BIT 0 PW1 Q Q PH1/ MUX BIT 1 PW2 Q PPOL2 PORT H PIN CONTROL PPOL3 Q PH2/ MUX BIT 2 PW3 Q Q PH3/ MUX BIT 3 PW4 Q PPOL4 MOTOROLA 63 ...
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... Channels 1 and 2 are concatenated to create one 16-bit PWM channel. PCKA[2:1] —Prescaler for Clock A (See also PWSCAL register) Determines the rate of clock A Bit 3 — Not implemented Always reads zero PCKB[3:1] — Prescaler for Clock B Determines the rate for clock B MOTOROLA PCKA2 PCKA1 — ...
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... Channel enabled MC68HC11KA4 MC68HC11KA4TS PCLK2 PCLK1 PPOL4 PPOL3 — — PWEN4 PWEN3 $0061 1 Bit 0 PPOL2 PPOL1 0 0 $0062 1 Bit $0063 1 Bit 0 PWEN2 PWEN1 0 0 MOTOROLA 65 ...
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... PWDTY[1:4] — Pulse-Width Modulation Timer Duty Cycle Bit 7 6 $006C Bit 7 6 $006D Bit 7 6 $006E Bit 7 6 $006F Bit 7 6 RESET PWDTY[1:4] Determines duty cycle of associated PWM channel MOTOROLA ...
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... MC68HC11KA4 MC68HC11KA4TS/D MOTOROLA 67 ...
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... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “ ...