HYB25D128323CL3.6 Infineon Technologies AG, HYB25D128323CL3.6 Datasheet
HYB25D128323CL3.6
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HYB25D128323CL3.6 Summary of contents
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... Edition 2003-07 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany Infineon Technologies AG 2003. © All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein ...
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HYB25D128323C[-3/-3.3], HYB25D128323C[-3.6/L3.6], HYB25D128323C[-4.5/L4.5], HYB25D128323C-5 Revision History: V1.7 Previous Version: V1.51 Page Subjects (major changes since last revision) all new data sheet template 43 AC Operation Conditions: Input Slew Rate added 46 Timing Parameters for speed sorts –3, –3.3, –3.6, –4.5, ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1 Ball Out 128Mbit DDR SGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] 7 V1.7, 2003-07 ...
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... Timing Parameters for speed sorts –3, –3.3, –3.6, –4.5, and – Table 18 Timing Parameters for speed sorts L3.6 and L4 Table 19 HYB25D128323C– Table 20 HYB25D128323C–3 Table 21 HYB25D128323C–3 Table 22 HYB25D128323C–4 Table 23 HYB25D128323C– Table 24 HYB25D128323CL3 Table 25 HYB25D128323CL4 Table 26 Operating Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] 8 V1.7, 2003-07 ...
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Mbit DDR SGRAM 1 Overview 1.1 Features • Maximum clock frequency up to 333 MHz • Maximum data rate up to 666 Mbps/pin • Data transfer on both edges of clock • Programmable CAS latency and ...
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SGRAM consists of a single 64-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding 32-bit wide, one-half clock cycle data transfers at the I/O pins. The result is a data rate of 666 Mbits ...
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Pin Configuration DQS DDQ DDQ DQS ...
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Table 2 Signal and Pin Description Pin IO Type Detailed Function CLK, CLK Input Clock: CLK and CLK# are differential clock inputs. All address and command inputs are latched on the crossing of the positive edge of CLK and the ...
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Table 2 Signal and Pin Description (cont’d) Pin IO Type Detailed Function DM3.. DM0 Input Input Data Mask: The DM signals are input mask signal for WRITE data. They mask off a complete byte on the data bus. DMx = ...
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Column Addresses A7-A0, AP Column Address Buffer Column Address Counter Row Decoder Memory Array Bank 0 4096 x 256 x 32 bit Figure 2 Functional blocks Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] Row Addresses A11-A0, BA1-BA0 Row Decoder Memory Array Bank 1 4096 ...
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Register Set 3.1 Mode Register The mode register stores the data for controlling the various operating modes of the DDR SGRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL ON and various vendor specific options. The ...
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Extended Mode Register Setup (EMRS) The Extended Mode Register is responsible for enabling / disabling the DLL in the HYB25D128323C and for selecting the interface type for the IOs and input pins. The Extended Mode Register can be programmed ...
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DQSx signals. During write bursts, the DQSx signal marks the center of the valid data window. Data is available at every rising and falling edge ...
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Table 4 Mapping of DQSx and DMx data strobe signal DQS0 DQS1 DQS2 DQS3 The minimum time during which the output data is valid is critical for the receiving device. This also applies to the Data Strobe DQS during a ...
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DQSx DMx DQx Figure 7 DQS and DM Timing at Write Prior to a burst of write data, given that the controller is not currently in burst write mode, the data strobe signal (DQSx) transits from Hi valid ...
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Description of Timings 3.5.1 Power-Up Sequence The following sequence is highly recommended for Power-Up: 1. Apply power and start clock. Maintain CKE=L and the other pins are in NOP conditions at the input 2. Apply V before or at ...
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Bank Activation Command (ACT) The Bank Activation command is initiated by issuing an ACT command at the rising edge of the clock. The DDR SGRAM has four independent banks which are selected by the two Bank select Addresses (BA0, ...
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Table 5 Precharge Control A8/AP BA1 Clk Command Addresses Figure 13 Precharge Command Timing 3.5.6 Self Refresh The self refresh mode can be used to retain the data in the ...
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Clk Command CKE Figure 14 Self Refresh timing 3.5.7 Auto Refresh The auto refresh function is initiated by issuing an Auto Refresh command at the rising edge of the clock. All banks must be precharged and idle before the Auto ...
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Clk Command PRE NOP CKE Power Down Mode entry Figure 16 Power Down Mode timing 3.5.9 Burst Mode Operation Burst mode operation is used to provide a constant flow of data to the memory (write cycle) or from the memory ...
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CLK Read Command DQSx CAS latency = 2 DQx DQSx CAS latency = 3 DQx DQSx CAS latency = 4 DQx Figure 17 Burst Read Operation 3.5.11 Burst Write Operation (WRITE) The Burst Write is initiated by issuing a WRITE ...
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CLK DQSx DQx Figure 18 Burst Write Operation 3.5.12 Burst Stop Command (BST) A Burst Stop is initiated by issuing a BURST STOP command at the rising edge of the clock. The Burst Stop Command has the fewest restrictions, making ...
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CLK READ BST Command DQSx CAS latency = 2 DQx DQSx CAS latency = 3 DQx DQSx CAS latency = 4 DQx Figure 19 Burst Stop for Read 3.5.13 Data Mask (DMx) Function The ...
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CLK WRITE NOP Command DQSx DQx DMx Figure 20 Data Mask Timing 3.5.14 Autoprecharge Operation The Autoprecharge command is issued by setting column address A8 high when a Read or a Write command is asserted to the DDR SGRAM. If ...
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CLK READA NOP Command DQSx CAS latency = 2 DQx DQSx CAS latency = 3 DQx DQSx CAS latency = 4 DQx Begin of Burst length = 4 ...
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Burst length = CLK BANK A NOP Command ACTIVATE t RCD(min) t RAS(min) DQSx DQx Figure 22 Read Concurrent Auto Precharge Table 7 Concurrent Read Auto Precharge Support Asserted For same Bank Command T4 READ NO READ+AP ...
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Burst length = CLK BANK A NOP Command ACTIVATE DQSx DQx Figure 23 Write Burst with Auto Precharge Note: t starts at the first rising edge of clock after the last valid edge of the 4 DQSx. ...
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Read command is satisfied. At this point, the data from the interrupting Read command appears. Read to Read interval (CAS#(a) to CAS#(b) Command period, CLK READ a Command t CCD DQSx DQx Figure 24 Read interrupted by Read 3.6.2 ...
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Read Interrupted by a Precharge A Burst Read operation can be interrupted by a Precharge of the same bank. The Read command to Precharge time is minimum 1 clock cycle. The Precharge command disables the data output depending on ...
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Write Interrupted by a Read A Burst Write can be interrupted by a Read command sent to any bank. The DQs must be in the high impedance state at least one clock cycle before the data of the interrupting ...
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CLK Write NOP Command bank A t DQSS DQSx DQx DMx Figure 29 Write interrupted by Precharge 3.7 Operations and Functions Table 9 Command Overview Operation Code Device Deselect DESEL No Operation NOP Mode Register Setup MRS Extended Mode Register ...
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Table 9 Command Overview (cont’d) Operation Code Power Down Mode Entry PWDNEN (Note) Power Down Mode Exit PWDNEX Note: The Power Down Mode Entry command is illegal during Burst Read or Burst Write operations. 3.8 Function Truth Tables Table 10 ...
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Table 11 Function Truth Table I (cont’d) Current State Command ROW ACTIVE DESEL NOP BST READ / READA WRITE / WRITEA ACT PRE / PREAL AREF / SREF MRS / EMRS READ DESEL NOP BST READ / READA WRITE / ...
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Table 11 Function Truth Table I (cont’d) Current State Command WRITE with DESEL Autoprecharge NOP BST READ / READA WRITE / WRITEA ACT PRE / PREAL AREF / SREF MRS / EMRS ROW DESEL ACTIVATING NOP BST READ / READA ...
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Table 11 Function Truth Table I (cont’d) Current State Command WRITE DESEL RECOVERING NOP with Auto- BST precharge READ / READA WRITE / WRITEA ACT PRE / PREAL AREF / SREF MRS / EMRS REFRESH DESEL NOP BST READ / ...
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Table 12 Function Truth Table for CKE Current CKE CKE CS# State n-1 n SELF REFRESH POWER H X ...
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DDR SGRAM Simplified State Diagram MODE MRS REGISTER SET WRITE WRITE WRITEA WRITEA POWER PRE ON Figure 30 DDR SGRAM Simplified State Diagram Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] SELF REFRESH SREFEN SREFEX AUTO AREF IDLE REFRESH CKEL CKEH ACT CKEH CKEL ...
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Electrical Characteristics Table 13 Absolute Maximum Ratings Parameter V Voltage on I/O pins relative Voltage on Inputs relative to SS Voltage on V supply relative Voltage on supply relative to DDQ Operating Temperature ...
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Under all conditions, must be less than or equal to DDQ 3) The speed sorts L3.6 and –3.6 support both 2.5 V ...
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Table 16 Pin Capacitances Pin DQ0.. DQ31, DQS0 .. DQS3 DM0.. DM3 Table 17 Timing Parameters for speed sorts –3, –3.3, –3.6, –4.5, and –5 Part Number Extension –3 Interface MIM Parameter Symbol min. max. min. max. min. max. min. ...
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Table 17 Timing Parameters for speed sorts –3, –3.3, –3.6, –4.5, and –5 (cont’d) Part Number Extension –3 Interface MIM Parameter Symbol min. max. min. max. min. max. min. max. min. max. — Read Cycle Timing Parameters for Data and ...
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Table 17 Timing Parameters for speed sorts –3, –3.3, –3.6, –4.5, and –5 (cont’d) Part Number Extension –3 Interface MIM Parameter Symbol min. max. min. max. min. max. min. max. min. max. — t Internal WRITE to 1 WTR READ ...
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Table 18 Timing Parameters for speed sorts L3.6 and L4.5 (cont’d) Part Number Extension Interface Parameter Clock low level width Minimum clock half period Command and Address Setup and Hold Times Address and Command input setup time Address and Command ...
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Table 18 Timing Parameters for speed sorts L3.6 and L4.5 (cont’d) Part Number Extension Interface Parameter Internal WRITE to READ command delay Write DQS High level Width Write DQS Low level Width Refresh Cycle Refresh Period (4096 cycles) Average periodic ...
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Table 20 HYB25D128323C–3.3 Frequency / t CAS latency CK 300 MHz / 3 278 MHz / 3 250 MHz / 4 222 MHz / 4 200 MHz / 5 Table ...
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... Table 24 HYB25D128323CL3.6 t Frequency / CAS latency CK 278 MHz / 3 250 MHz / 4 222 MHz / 4 200 MHz / 5 166 MHz / 6 Table 25 HYB25D128323CL4.5 t Frequency / CAS latency CK 222 MHz / 4 200 MHz / 5 183 MHz / 5 166 MHz / 6 143 MHz / 7 Table 26 Operating Currents Parameter & ...
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Table 26 Operating Currents (cont’d) Parameter & Test Condition IDLE STANDBY CURRENT: CKE=HIGH; CS#=HIGH (DESELECT); All banks idle Address and control CK CK(min.) inputs changing once per clock cycle for DQ, DQS and ...
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Package Outlines Module Package The package is conforming with JEDEC MO-205 Variation BD General Tolerances according to ISO 8015 The inner matrix of 4 × 4 balls is reserved for thermal contacts 1.50 1.44 1.36 0 ...
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... Published by Infineon Technologies AG ...