W77E58P-40 Winbond, W77E58P-40 Datasheet
W77E58P-40
Available stocks
Related parts for W77E58P-40
W77E58P-40 Summary of contents
Page 1
Table of Contents-- GENERAL DESCRIPTION ..............................................................................................................................2 FEATURES......................................................................................................................................................2 PIN CONFIGURATION ....................................................................................................................................3 PIN DESCRIPTION..........................................................................................................................................4 BLOCK DIAGRAM ...........................................................................................................................................6 FUNCTIONAL DESCRIPTION ........................................................................................................................7 MEMORY ORGANIZATION.............................................................................................................................8 INSTRUCTION...........................................................................................................................................29 INSTRUCTION TIMING .............................................................................................................................37 POWER MANAGEMENT ..........................................................................................................................46 RESET CONDITIONS................................................................................................................................48 RESET STATE...........................................................................................................................................49 PROGRAMMABLE TIMERS/COUNTERS ....................................................................................................53 TIMED ACCESS PROTECTION ...................................................................................................................70 ON-CHIP MTP ...
Page 2
... Two enhanced full duplex serial ports 32 KB flash Multiple-Time Programmable(MTP) ROM 256 bytes scratch-pad RAM 1 KB on-chip SRAM for MOVX instruction Programmable Watchdog Timer Dual 16-bit Data Pointers Software programmable access cycle to external RAM/peripherals Packages: DIP 40: W77E58-25/40 PLCC 44: W77E58P-25/40 QFP 44: W77E58F-25/40 Preliminary W77E58 - 2 - ...
Page 3
... PIN CONFIGURATION 40-Pin DIP (W77E58) 44-Pin PLCC (W77E58P INT3, P1.5 8 INT4, P1.6 9 INT5, P1.7 10 RST 11 RXD, P3.0 P4 ...
Page 4
PIN DESCRIPTION SYMBOL TYPE I EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of EA external ROM. It should be kept high to access internal ROM. The ROM address and data will not be present on the ...
Page 5
Pin Description, continued SYMBOL TYPE I/O PORT 3: Port bi-directional I/O port with internal pull-ups. All bits have P3.0 P3.7 alternate functions, which are described below: RXD(P3.0) : Serial Port 0 input TXD(P3.1) : Serial Port 0 ...
Page 6
BLOCK DIAGRAM P1.0 Port Port 1 1 P1.7 Latch Interrupt Timer 2 Timer 0 Timer 1 2 UARTs Port 3 Port P3.0 Latch 3 P3.7 Port 4 Latch P4.0 Port 4 Oscillator P4.3 XTAL1 XTAL2 Preliminary W77E58 ACC B T1 ...
Page 7
FUNCTIONAL DESCRIPTION The W77E58 is 8052 pin compatible and instruction set compatible. It includes the resources of the standard 8052 such as four 8-bit I/O Ports, three 16-bit timer/counters, full duplex serial port and interrupt sources. The W77E58 features a ...
Page 8
Timers: The W77E58 has three 16-bit timers that are functionally similar to the timers of the 8052 family. When used as timers, they can be set to run at either 4 clocks or 12 clocks per count, thus providing the ...
Page 9
Data Memory: The W77E58 can access up to 64Kbytes of external Data Memory. This memory region is accessed by the MOVX instructions. Unlike the 8051 derivatives, the W77E58 contains on-chip 1K bytes MOVX SRAM of Data Memory, which can only ...
Page 10
FFh Indirect RAM 80h 7Fh Direct RAM 30h 2Fh 2Eh 2Dh 2Ch 2Bh 2Ah 29h 4F ...
Page 11
Special Function Registers The W77E58 uses Special Function Registers (SFRs) to control and monitor peripherals and their Modes. The SFRs reside in the register locations 80-FFh and are accessed by direct addressing only. Some of the SFRs are bit addressable. ...
Page 12
A brief description of the SFRs now follows. PORT 0 Bit: 7 P0.7 Mnemonic: P0 Port open-drain bi-directional I/O port. This port also provides a multiplexed low order address/data bus during accesses to external memory. STACK POINTER ...
Page 13
This is the low byte of the new additional 16-bit data pointer that has been added to the W77E58. The user can switch between DPL, DPH and DPL1, DPH1 simply by setting register DPS = 1. The instructions that use ...
Page 14
TIMER CONTROL Bit: 7 TF1 Mnemonic: TCON TF1: Timer 1 overflow flag: This bit is set when Timer 1 overflows cleared automatically when the program does a timer 1 interrupt service routine. Software can also set or clear ...
Page 15
M1, M0: Mode Select bits Mode 0 0 Mode 0: 8-bits with 5-bit prescale Mode 1: 18-bits, no prescale Mode 2: 8-bits with auto-reload from THx 1 1 Mode 3: (Timer 0) TL0 is ...
Page 16
CLOCK CONTROL Bit: 7 WD1 Mnemonic: CKCON WD1-0: Watchdog timer mode select bits: These bits determine the time-out period for the watchdog timer. In all four time-out options the reset time-out is 512 clocks more than the interrupt time- out ...
Page 17
PORT 1 Bit: 7 P1.7 Mnemonic: P1 P1.7-0: General purpose I/O port. Most instructions will read the port pins in case of a port read access, however in case of read-modify-write instructions, the port latch is read. Some pins also ...
Page 18
SERIAL PORT CONTROL Bit: 7 SM0/FE Mnemonic: SCON SM0/FE: Serial port 0, Mode 0 bit or Framing Error Flag: The SMOD0 bit in PCON SFR determines whether this bit acts as SM0 or as FE. The operation of SM0 is ...
Page 19
SERIAL DATA BUFFER Bit: 7 SBUF.7 SBUF.6 SBUF.5 SBUF.4 SBUF.3 SBUF.2 SBUF.1 SBUF.0 Mnemonic: SBUF SBUF.7-0: Serial data on the serial port 0 is read from or written to this location. It actually consists of two separate internal 8-bit registers. ...
Page 20
SLAVE ADDRESS Bit: 7 Mnemonic: SADDR SADDR: The SADDR should be programmed to the given or broadcast address for serial port 0 to which the slave processor is designated. SLAVE ADDRESS 1 Bit: 7 Mnemonic: SADDR1 SADDR1: The SADDR1 should ...
Page 21
IP.7: This bit is un-implemented and will read high. PS1: This bit defines the Serial port 1 interrupt priority sets it to higher priority level. PT2: This bit defines the Timer 2 interrupt priority. PT2 = 1 ...
Page 22
SM1_1: Serial port 1 Mode bit 1: SM0_1 SM1_1 Mode SM2_1:Multiple processors communication. Setting this bit to 1 enables the multiprocessor communication feature in mode 2 and 3. In mode 2 or ...
Page 23
WS: Wait State Signal Enable. Setting this bit enables the WAIT signal on P4.0. The device will sample the wait state control signal WAIT via P4.0 during MOVX instruction. This bit is time access protected. POWER MANAGEMENT REGISTER Bit: 7 ...
Page 24
STATUS REGISTER Bit Mnemonic: STATUS HIP: High Priority Interrupt Status. When set, it indicates that software is servicing a high priority interrupt. This bit will be cleared when the program executes the corresponding RETI instruction. LIP: Low Priority ...
Page 25
TIMER 2 CONTROL Bit: 7 TF2 Mnemonic: T2CON TF2: Timer 2 overflow flag: This bit is set when Timer 2 overflows also set when the count is equal to the capture register in down count mode. It can ...
Page 26
HC5: Hardware Clear INT5 flag. Setting this bit allows the flag of external interrupt automatically cleared by hardware while entering the interrupt service routine. HC4: Hardware Clear INT4 flag. Setting this bit allows the flag of external ...
Page 27
TIMER 2 MSB Bit: 7 TH2.7 Mnemonic: TH2 TH2: Timer 2 MSB PROGRAM STATUS WORD Bit Mnemonic: PSW CY: Carry flag: Set for an arithmetic operation which results in a carry being generated from the ALU ...
Page 28
WTRF: Watchdog Timer Reset Flag. Hardware will set this bit when the watchdog timer causes a reset. Software can read it but must clear it manually. A power-fail reset will also clear the bit. This bit helps software in determining ...
Page 29
B REGISTER Bit: 7 B.7 Mnemonic: B B.7-0:The B register is the standard 8052 register that serves as a second accumulator. EXTENDED INTERRUPT PRIORITY Bit Mnemonic: EIP EIP.7-5:Reserved bits. PWDI: Watchdog timer interrupt priority. PX5: External Interrupt 5 ...
Page 30
Table 2. Instructions that affect Flag settings Instruction Carry Overflow ADD X X ADDC X X SUBB X X MUL 0 X DIV RRC A X RLC A X SETB "X" indicates ...
Page 31
Table 3. Instruction Timing for W77E58, continued Instruction HEX Op-Code ADDC A, @R0 36 ADDC A, @R1 37 ADDC A, direct 35 ADDC A, #data 34 ACALL addr11 71,91,B1, 11,31,51, D1,F1 AJMP ADDR11 01,21,41, 61,81,A1, C1,E1 ANL ...
Page 32
Table 3. Instruction Timing for W77E58, continued Instruction HEX Op-Code CLR A E4 CPL A F4 CLR C C3 CLR bit C2 CPL C B3 CPL bit B2 DEC A 14 DEC R0 18 DEC R1 19 DEC R2 1A ...
Page 33
Table 3. Instruction Timing for W77E58, continued Instruction HEX Op-Code INC R6 0E INC R7 0F INC @R0 06 INC @R1 07 INC direct 05 INC DPTR A3 JMP @A+DPTR 73 JZ rel 60 JNZ rel 70 JC rel 40 ...
Page 34
Table 3. Instruction Timing for W77E58, continued Instruction HEX Op-Code MOV R1, direct A9 MOV R2, direct AA MOV R3, direct AB MOV R4, direct AC MOV R5, direct AD MOV R6, direct AE MOV R7, direct AF MOV R0, ...
Page 35
Table 3. Instruction Timing for W77E58, continued Instruction HEX Op-Code MOVX A, @R0 E2 MOVX A, @R1 E3 MOVX A, @DPTR E0 MOVX @R0 MOVX @R1 MOVX @DPTR MOV C, bit A2 MOV bit, ...
Page 36
Table 3. Instruction Timing for W77E58, continued Instruction HEX Op-Code SUBB SUBB SUBB SUBB SUBB SUBB SUBB A, @R0 96 SUBB A, ...
Page 37
INSTRUCTION TIMING The instruction timing for the W77E58 is an important aspect, especially for those users who wish to use software instructions to generate timing delays. Also, it provides the user with an insight into the timing differences between the ...
Page 38
Instruction Fetch C1 C2 CLK ALE PSEN PC AD7-0 PORT 2 Instruction Fetch CLK ALE PSEN A7-0 OP-CODE AD7-0 PORT 2 Address A15-8 Figure 5. Three Cycle Instruction Timing Preliminary W77E58 Operand Fetch OP-CODE ...
Page 39
Instruction Fetch CLK ALE PSEN OP-CODE AD7-0 A7-0 Port 2 Address A15-8 Instruction Fetch Operand Fetch CLK ALE PSEN A7-0 OP-CODE AD7-0 Address A15-8 PORT 2 Operand Fetch Operand Fetch C1 ...
Page 40
MOVX Instruction The W77E58, like the standard 8032, uses the MOVX instruction to access external Data Memory. This Data Memory includes both off-chip memory as well as memory mapped peripherals. While the results of the MOVX instruction are the same ...
Page 41
Machine cycles in standard 8032 = 10 + (26 * CNT) Machine cycles in W77E58 = 10 + (26 * CNT) If CNT = 50 Clock cycles in standard 8032= ((10 + (26 *50 (10 + 1300) ...
Page 42
CPU was held for the desired period. There is no effect on any other instruction or its timing. By default, the Stretch value is set at 1, giving a MOVX instruction of 3 machine cycles. If desired by ...
Page 43
Last Cycle First of Previous Machine Cycle Instruction CLK ALE PSEN WR D0-D7 A0-A7 A0-A7 PORT 0 MOVX Inst. Next Inst. Address Address MOVX Inst. PORT 2 A15-A8 Figure 9. Data Memory Write with ...
Page 44
Last Cycle of Previous Instruction CLK ALE PSEN WR D0-D7 A0-A7 PORT 0 MOVX Inst. Address MOVX Inst. PORT 2 A15-A8 Wait State Control Signal Either with the software using stretch value to change the required ...
Page 45
Wait State Control Signal Timing ( when Stretch = 1 ) First Machine Cycle CLOCK ALE PSEN ADDRESS WAIT Wait State Control Signal Timing ( when Stretch = 2 ) First Machine Cycle ...
Page 46
POWER MANAGEMENT The W77E58 has several features that help the user to control the power consumption of the device. The power saving features are basically the POWER DOWN mode, ECONOMY mode and the IDLE mode of operation. Idle Mode The ...
Page 47
The selection of instruction rate is going to take effect after a delay of one instruction cycle. Switching to divide 1024 mode must first go from divide by 4 mode. This means software can not switch directly ...
Page 48
The W77E58 can be woken from the Power Down mode by forcing an external interrupt pin activated, provided the corresponding interrupt is enabled, while the global enable(EA) bit is set and the external input has been set to a level ...
Page 49
The software must clear the POR flag after reading it, otherwise it will not be possible to correctly determine future reset sources. If the power fails, i.e. falls below Vrst, then the device will once again go into reset state. ...
Page 50
Table 6. SFR Reset Value, continued SFR Name Reset Value SCON 00000000b SBUF xxxxxxxx P2 11111111b SADDR1 00000000b SCON1 00000000b ROMMAP xxx 01 EXIF 0000 P4 xxxx The WDCON SFR bits are set/cleared in reset condition depending on the source ...
Page 51
The Timer 0 and 1 Interrupts are generated by the TF0 and TF1 flags. These flags are set by the overflow in the Timer 0 and Timer 1. The TF0 and TF1 flags are automatically cleared by the hardware when ...
Page 52
The interrupt flags are sampled every machine cycle. In the same machine cycle, the sampled interrupts are polled and their priority is resolved. If certain conditions are met then the hardware will execute an internally generated LCALL instruction which will ...
Page 53
Execution continues from the vectored address till an RETI instruction is executed. On execution of the RETI instruction the processor pops the Stack and loads the PC with the contents at the top of the stack. The user must take ...
Page 54
When configured as a "Timer", the timer counts clock cycles. The timer clock can be programmed to be thought of as 1/12 of the system clock or 1/4 of the system clock. In the "Counter" mode, the register is incremented ...
Page 55
T0M = CKCON.3 (T1M = CKCON.4) Clock Source Mode input 1/4 div osc/1 div osc/16 div. by 1024 osc/256 1/ P3.4 (T1 = P3.5) TR0 = TCON.4 (TR1 = TCON.6) GATE = TMOD.3 (GATE ...
Page 56
T0M = CKCON.3 (T1M = CKCON.4) Clock Source Mode input 1/4 div osc/1 div osc/16 div. by 1024 osc/256 1/ P3.4 (T1 = P3.5) TR0 = TCON.4 (TR1 = TCON.6) GATE = TMOD.3 (GATE ...
Page 57
T0M = CKCON.3 Clock Source 1/4 Mode input div osc/1 div osc/16 1/12 div. by 1024 osc/256 T0 = P3.4 TR0 = TCON.4 GATE = TMOD.3 INT0 = P3.2 TR1 = TCON.6 CAPTURE MODE The capture ...
Page 58
AUTO-RELOAD MODE, COUNTING UP The auto-reload mode counter is enabled by clearing the CP RL and clearing the DCEN bit in T2MOD register. In this mode, Timer/Counter bit up counter. When the counter ...
Page 59
T2M = CKCON.5 Clock Source Mode input 1/4 1 div osc/1 div osc/16 div. by 1024 osc/256 1/ P1.0 TR2 = T2CON.2 T2EX = P1.1 BAUD RATE GENERATOR MODE The baud rate generator ...
Page 60
PROGRAMMABLE CLOCK-OUT Timer 2 is equipped with a new clock-out feature which outputs a 50% duty cycle clock on P1.0. It can be invoked as a programmable clock generator. To configure Timer 2 with clock-out mode, software must initiate it ...
Page 61
Clock Source Mode input div osc/1 div osc/16 17 div. by 1024 osc/256 20 Reset Watchdog 23 RWT (WDCON.0) The Watchdog timer should first be restarted by using RWT. This ensures that the timer starts ...
Page 62
The main use of the Watchdog timer system monitor. This is important in real-time control applications. In case of some power glitches or electro-magnetic interference, the processor may begin to execute errant code. If this is left ...
Page 63
RWT: WDCON.0 - Reset Watchdog Timer. This bit is used to clear the Watchdog timer and to restart it. This bit is self-clearing, so after the software writes the hardware will automatically clear it. If the Watchdog ...
Page 64
Clock Source Mode input div osc/1 div osc/16 div. by 1024 osc/256 Write to SBUF START TX CLOCK SM2 CLOCK RI RX START REN RXD P3.0 Alternate Iutput function The ...
Page 65
Transmission begins with a write to SBUF. The serial data is brought out on to TxD pin at C1 following the first roll-over of divide by 16 counter. The next bit is placed on TxD pin at C1 following the ...
Page 66
Timer 1 Timer 2 Overflow Overflow (for Serial Port 0 only) 2 SMOD (SMOD_1) TCLK RCLK SAMPLE 1-TO-0 DETECTOR RXD MODE 2 This mode uses a total of 11 bits in asynchronous ...
Page 67
Clock Source Mode input div osc/2 div osc/32 div. by 1024 osc/512 Write to 2 SMOD (SMOD_1 SAMPLE 1-TO-0 DETECTOR RXD If the first bit detected after the falling edge of RxD ...
Page 68
MODE 3 This mode is similar to Mode 2 in all respects, except that the baud rate is programmable. The user must first initialize the Serial related SFR SCON before any communication can take place. This involves selection of the ...
Page 69
Framing Error Detection A Frame Error occurs when a valid stop bit is not detected. This could indicate incorrect serial data communication. Typically the frame error is due to noise and contention on the serial communication line. The W77E58 has ...
Page 70
The following example shows how the user can define the Given Address to address different slaves. Slave 1: SADDR1010 0100 SADEN 1111 1010 Given 1010 0x0x Slave 2: SADDR1010 0111 SADEN 1111 1001 Given 1010 0xx1 The Given address for ...
Page 71
When the software writes AAh to the TA SFR, a counter is started. This counter waits for 3 machine cycles looking for a write of 55h to TA. If the second write (55h) occurs within 3 machine cycles of the ...
Page 72
READ OPERATION This operation is supported for customer to read their code and the Security bits. The data will not be valid if the Lock bit is programmed to low. OUTPUT DISABLE CONDITION When the OE is set to high, ...
Page 73
Operations P3.0 P3.1 (A9 (A13 CTRL) CTRL) Read 0 0 Output Disable 0 0 Program 0 0 Program Verify 0 0 Erase 1 0 Erase Verify 1 0 Program/Erase X 0 Inhibit Company Device ...
Page 74
SECURITY BITS During the on-chip MTP ROM operation mode, the MTP ROM can be programmed and verified repeatedly. Until the code inside the MTP ROM is confirmed OK, the code can be protected. The protection of MTP ROM and those ...
Page 75
B0:Lock bit This bit is used to protect the customer's program code in the W77E58. It may be set after the programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the MTP ROM ...
Page 76
DC ELECTRICAL CHARACTERISTICS ( 10 Fosc = 20 MHz, unless otherwise specified PARAMETER SYMBOL Operating Voltage Operating Current Idle Current Power Down Current Input Current P1, P2, P3 [*1] Input ...
Page 77
Notes:*1. RST pin is a Schmitt trigger input. *2. P0, ALE and PSEN are tested in the external access mode. *3. XTAL1 is a CMOS input. *4. Pins of P1, P2, P3 can source a transition current when they are ...
Page 78
AC Specification, continued PARAMETER PSEN Low to Valid Instruction In Input Instruction Hold After PSEN Input Instruction Float After PSEN Port 0 Address to Valid Instr. In Port 2 Address to Valid Instr. In PSEN Low to Address Float Data ...
Page 79
Movx Characteristics Using Strech Memory Cycles, continued PARAMETER RD WR ALE Low to or Low RD WR Port 0 Address to or Low RD WR Port 2 Address to or Low Data Valid to WR Transition Data Hold after Write ...
Page 80
Time C Clock H Logic level high I Instruction Q Output Data V Valid X No longer a valid state PROGRAM MEMORY READ CYCLE t LHLL ALE t AVLL PSEN ADDRESS PORT 0 A0-A7 PORT 2 A Address D ...
Page 81
DATA MEMORY READ CYCLE ALE PSEN RD PORT 0 INSTRUCTION IN PORT 2 DATA MEMORY WRITE CYCLE ALE PSEN WR PORT 0 INSTRUCTION IN PORT 2 t LLDV t LLWL t RLRH t LLAX1 t RLDV t AVLL t RLAZ ...
Page 82
TYPICAL APPLICATION CIRCUITS Expanded External Program Memory and Crystal XTAL1 XTAL2 CRYSTAL 8 RST C1 C2 INT0 12 13 INT1 P1.0 2 P1.1 ...
Page 83
Expanded External Data Memory and Oscillator OSCILLATOR 8 PACKAGE DIMENSIONS 40-pin DIP ...
Page 84
PLCC Seating Plane 44-pin QFP See Detail F Seating Plane 40 39 ...
Page 85
... No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 Note: All data and specifications are subject to change without notice. Preliminary W77E58 Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. ...