UPD70F3114GC-8EU NEC, UPD70F3114GC-8EU Datasheet
UPD70F3114GC-8EU
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User’s Manual V850E/IA2 32-Bit Single-Chip Microcontrollers Hardware µ PD703114 µ PD703114(A) µ PD70F3114 µ PD70F3114(A) Document No. U15195EJ5V0UD00 (5th edition) Date Published August 2005 N CP(K) 2001 Printed in Japan ...
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User’s Manual U15195EJ5V0UD ...
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... HANDLING OF UNUSED INPUT PINS 2 Unconnected CMOS device inputs can be cause of malfunction input pin is unconnected possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry ...
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... NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. • ...
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... Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • ...
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Readers This manual is intended for users who wish to understand the functions of the V850E/IA2 and design application systems using it. The target products are as follows. • Standard products: • Special grade products: Purpose This manual is intended ...
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To understand the overall functions of the V850E/IA2 → Read this manual according to the CONTENTS. • How to read register formats → The name of a bit whose number is in angle brackets (<>) is defined as a ...
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Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850E/IA2 V850E1 Architecture User’s Manual V850E/IA2 Hardware User’s Manual V850E/IA1, V850E/IA2 AC Motor Inverter Control Using ...
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... Configuration of Function Block............................................................................................. 25 1.6.1 Internal block diagram ..................................................................................................................25 1.6.2 Internal units.................................................................................................................................26 CHAPTER 2 PIN FUNCTIONS ................................................................................................................28 2.1 List of Pin Functions ................................................................................................................ 28 2.2 Pin Status................................................................................................................................... 33 2.3 Description of Pin Functions ................................................................................................... 34 2.4 Types of Pin I/O Circuits and Connection of Unused Pins................................................... 43 2.5 Pin I/O Circuits .......................................................................................................................... 45 CHAPTER 3 CPU FUNCTION.................................................................................................................46 3.1 Features ..................................................................................................................................... 46 3.2 CPU Register Set ...................................................................................................................... 47 3.2.1 Program register set.....................................................................................................................48 3.2.2 System register set.......................................................................................................................49 3.3 Operation Modes ...
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Chip select control function.......................................................................................................... 82 4.4 Bus Cycle Type Control Function ........................................................................................... 85 4.5 Bus Access ................................................................................................................................ 86 4.5.1 Number of access clocks............................................................................................................. 86 4.5.2 Bus sizing function....................................................................................................................... 87 4.5.3 Bus width ..................................................................................................................................... 88 4.6 Wait Function............................................................................................................................. 94 4.6.1 ...
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Forcible Termination .............................................................................................................. 129 6.12.1 Restrictions on forcible termination of DMA transfer ..................................................................130 6.13 Time Required for DMA Transfer .......................................................................................... 131 6.14 Cautions................................................................................................................................... 132 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION..................................................134 7.1 Features ................................................................................................................................... 134 7.2 Non-Maskable Interrupt.......................................................................................................... 138 7.2.1 Operation ...
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... Operation................................................................................................................................... 380 9.4.7 Application examples................................................................................................................. 388 9.4.8 Cautions .................................................................................................................................... 394 9.5 Timer 4...................................................................................................................................... 395 9.5.1 Features (timer 4) ...................................................................................................................... 395 9.5.2 Function overview (timer 4) ....................................................................................................... 395 9.5.3 Basic configuration .................................................................................................................... 396 9.5.4 Control register .......................................................................................................................... 400 9.5.5 Operation................................................................................................................................... 401 9.5.6 Application example .................................................................................................................. 403 9.5.7 Cautions .................................................................................................................................... 403 9.6 Timer Connection Function ................................................................................................... 404 9.6.1 Overview.................................................................................................................................... 404 9.6.2 Control register .......................................................................................................................... 405 12 User’s Manual U15195EJ5V0UD ...
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CHAPTER 10 SERIAL INTERFACE FUNCTION ................................................................................406 10.1 Features ................................................................................................................................... 406 10.1.1 Selecting UART1 or CSI1 mode.................................................................................................407 10.2 Asynchronous Serial Interface 0 (UART0) ........................................................................... 408 10.2.1 Features .....................................................................................................................................408 10.2.2 Configuration ..............................................................................................................................409 10.2.3 Control registers .........................................................................................................................411 10.2.4 Interrupt requests .......................................................................................................................418 10.2.5 Operation ...
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... Timer 10, timer 3 input pins ....................................................................................................... 581 12.5.3 Timer 2 input pins ...................................................................................................................... 585 12.6 Cautions..................................................................................................................................... 588 12.6.1 Hysteresis characteristics .......................................................................................................... 588 CHAPTER 13 RESET FUNCTION........................................................................................................ 589 13.1 Features ................................................................................................................................... 589 13.2 Pin Functions........................................................................................................................... 589 13.3 Initialization.............................................................................................................................. 594 CHAPTER 14 REGULATOR ................................................................................................................. 599 14.1 Features ................................................................................................................................... 599 14.2 Functional Outline................................................................................................................... 599 14.3 Connection Example............................................................................................................... 600 14.4 Control Register ...................................................................................................................... 602 14 User’s Manual U15195EJ5V0UD ...
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... CHAPTER 15 FLASH MEMORY ( 15.1 Features ................................................................................................................................... 603 15.2 Writing Using Flash Programmer.......................................................................................... 603 15.3 Programming Environment.................................................................................................... 606 15.4 Communication Mode ............................................................................................................ 606 15.5 Pin Connection........................................................................................................................ 608 15.5.1 MODE1/V pin ..........................................................................................................................608 PP 15.5.2 Serial interface pin......................................................................................................................608 15.5.3 RESET pin .................................................................................................................................610 15.5.4 NMI pin.......................................................................................................................................610 15.5.5 MODE0, MODE1 pins ................................................................................................................610 15.5.6 Port pins .....................................................................................................................................610 15.5.7 Other signal pins ........................................................................................................................610 15 ...
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CHAPTER 18 RECOMMENDED SOLDERING CONDITIONS........................................................... 662 APPENDIX A NOTES ON TARGET SYSTEM DESIGN ................................................................... 664 APPENDIX B REGISTER INDEX ......................................................................................................... 666 APPENDIX C INSTRUCTION SET LIST ............................................................................................. 675 C.1 Conventions............................................................................................................................. 675 C.2 Instruction Set (Alphabetical Order) ..................................................................................... 678 APPENDIX D ...
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... The V850E/IA2 is a product in NEC Electronics’ V850 Series of single-chip microcontrollers. This chapter provides an overview of the V850E/IA2. 1.1 Outline The V850E/IA2 is a 32-bit single-chip microcontroller that uses high-speed operations to realize high-precision inverter control of motors. It uses the V850E1 CPU of the V850 Series and has on-chip peripheral functions such as ROM, RAM, a bus interface, a DMA controller, timers including a 3-phase sine-wave PWM timer for motors, serial interfaces, and A/D converters ...
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... DD REF Supply voltage Package Note The maximum operating frequency of the in-circuit emulator is 40 MHz. A frequency of 50 MHz can be supported by upgrading the in-circuit emulator, so contact an NEC Electronics sales representative or distributor. Remark For details, refer to the user’s manual of each product. 18 CHAPTER 1 INTRODUCTION ...
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Table 1-2. Differences Between V850E/IA1 and V850E/IA2 Register Setting Values Register Name System wait control register (VSWC) Timer 1/timer 2 clock selection register (PRM02) Remark For details, refer to the user’s manual of each product. 1.2 Features Number of instructions ...
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... A/D converter: 6 channels + 8 channels (2 units) Regulator Two power supplies, one for the internal CPU and one for the peripheral interface, are not necessary single-power-supply system can be configured by connecting an N-ch transistor (2SD1950 (VL standard product, surface mount type) or 2SD1581 (independent type) is recommended 3.3 V power supply is available, it can be directly connected to the REGIN pin. Multiplication function (× ...
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Applications µ • PD703114, 70F3114: Consumer equipment (inverter air conditioners) Industrial equipment (motor control, general-purpose inverters) • µ PD703114(A), 70F3114(A): Automobile applications (electrical power steering) 1.4 Ordering Information Part Number µ 100-pin plastic LQFP (fine pitch) (14 × 14) ...
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Pin Configuration (Top View) • 100-pin plastic LQFP (fine pitch) (14 × 14) µ PD703114GC-×××-8EU µ PD703114GC-×××-8EU-A µ PD703114GC(A)-×××-8EU µ PD703114GC(A)-×××-8EU-A ANI05 DD1 AV 3 SS1 ANI10 4 ANI11 5 ANI12 6 ANI13 7 ANI14 8 ...
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QFP (14 × 20) µ µ PD703114GF-×××-3BA PD70F3114GF-3BA µ µ PD703114GF-×××-3BA-A PD70F3114GF-3BA-A 1 ANI03 2 ANI04 3 ANI05 4 AV DD1 5 AV SS1 6 ANI10 7 ANI11 8 ANI12 9 ANI13 10 ANI14 11 ANI15 12 ...
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Pin Identification A16 to A21: Address bus AD0 to AD15: Address/data bus ADTRG0, ADTRG1: A/D trigger input ANI00 to ANI05, ANI10 to ANI17: Analog input ASCK1: Asynchronous serial clock ASTB: Address strobe Analog power supply DD0 ...
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Configuration of Function Block 1.6.1 Internal block diagram NMI INTP2, INTP3 INTC INTP0/ESO0, INTP1/ESO1, INTP4/TO3OFF, INTP20/TI2, INTP21/TO21 to INTP24/TO24, Timer 0: INTP25/TCLR2, TM00, TM01 INTP30/TI3/TCLR3, Timer 1: TM10 INTP31/TO3, Timer 2: INTP100/TCUD10, TM20, TM21 INTP101/TCLR10 Timer 3: TM3 TO000 ...
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... PLL) the input clock (f resonator to pins X1 and X2 (only when using the on-chip PLL synthesizer) or input an external clock from the X1 pin. 26 CHAPTER 1 INTRODUCTION µ PD70F3114 includes flash memory (128 KB the internal system clock ( the input clock, connect an external X XX User’s Manual U15195EJ5V0UD ...
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Timer/counter function This unit incorporates a 2-channel 16-bit timer (TM0) for 3-phase sine wave PWM inverter control channel 16-bit up/down counter (TM1) that can be used for 2-phase encoder input general-purpose timer, a 2-channel ...
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The names and functions of the V850E/IA2 pins are shown below. These pins can be divided by function into port pins and non-port pins. 2.1 List of Pin Functions (1) Port pins Pin Name I/O P00 Input Port 0 6-bit ...
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Pin Name I/O PCT0 I/O Port CT 4-bit I/O port PCT1 Input or output can be specified in 1-bit units PCT4 PCT6 PDH0 I/O Port DH 6-bit I/O port PDH1 Input or output can be specified in 1-bit units PDH2 ...
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Non-port pins Pin Name I/O TO000 Output Timer 00 pulse signal output TO001 TO002 TO003 TO004 TO005 TO010 Output Timer 01 pulse signal output TO011 TO012 TO013 TO014 TO015 TO10 Output Timer 10 pulse signal output TO21 Output Timer ...
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... A16 to A21 Output Higher 6-bit address bus for external memory RESET Input System reset input X1 Input Crystal resonator connection pin for system clock oscillation. Input to X1 pin when providing clocks from outside. − X2 µ Note PD70F3114 only CHAPTER 2 PIN FUNCTIONS Function User’ ...
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Pin Name I/O CLKOUT Output System clock output CKSEL Input Input specifying clock generator operation mode − Positive power supply for A/D converter DD0 DD1 − Ground potential for A/D converter SS0 SS1 − ...
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Pin Status The following table shows the status of each pin after a reset, in power-saving mode (software STOP mode, IDLE, HALT), and during a DMA transfer. Operating Status Pin (Single-Chip Mode) A16 to A21 (PDH0 to PDH5) AD0 ...
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Description of Pin Functions (1) P00 to P05 (Port 0) … Input P00 to P05 function as a 6-bit input-only port in which all pins are fixed to input. Besides functioning as an input port, in control mode, P00 ...
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P10 to P12 (Port 1) … I/O P10 to P12 function as a 3-bit I/O port in which input or output can be set in 1-bit units. Besides functioning as an I/O port, in control mode, P10 to P12 ...
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P20 to P27 (Port 2) … I/O P20 to P27 function as an 8-bit I/O port in which input or output can be set in 1-bit units. Besides functioning as an I/O port, in control mode, P20 to P27 ...
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P30 to P34 (Port 3) … I/O P30 to P34 function as a 5-bit I/O port in which input or output can be set in 1-bit units. Besides functioning as an I/O port, in control mode, P30 to P34 ...
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P40 to P42 (Port 4) … I/O P40 to P42 function as a 3-bit I/O port in which input or output can be set in 1-bit units. Besides functioning as an I/O port, in control mode, P40 to P42 ...
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PCT0, PCT1, PCT4, PCT6 (Port CT) … I/O PCT0, PCT1, PCT4, and PCT6 function as a 4-bit I/O port in which input or output can be set in 1-bit units. Besides functioning as a port, in control mode, these ...
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PDH0 to PDH5 (Port DH) … I/O PDH0 to PDH5 function as a 6-bit I/O port in which input or output can be set in 1-bit units. Besides functioning as a port, in control mode (external expansion mode), these ...
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... Besides a normal initialize or start, this signal is also used to release a standby mode (HALT, IDLE, software STOP). (16) X1, X2 (Crystal) These pins connect a resonator for system clock generation. They can also input external clocks. In this case, connect the external clock to the X1 pin and leave the X2 pin open. (17) CV (Ground for clock generator) SS This is the ground pin for the resonator, PLL and regulator ...
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RV (Regulator power supply) DD This is the positive power supply pin for the regulator. Supply 5 V system power to this pin. (21) V (Ground) SS3 This is the internal 3.3 V system ground pin. (22) REGOUT (Regulator ...
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... Types of Pin I/O Circuits and Connection of Unused Pins Connection kΩ resistor is recommended when connecting to V Pin P00/NMI P01/ESO0/INTP0 P02/ESO1/INTP1 P03/ADTRG0/INTP2 P04/ADTRG1/INTP3 P05/INTP4/TO3OFF P10/TIUD10/TO10 P11/TCUD10/INTP100 P12/TCLR10/INTP101 P20/TI2/INTP20 P21/TO21/INTP21 to P24/TO24/INTP24 P25/TCLR2/INTP25 P26/TI3/TCLR3/INTP30 P27/TO3/INTP31 P30/RXD0 P31/TXD0 P32/RXD1/SI1 P33/TXD1/SO1 P34/ASCK1/SCK1 P40/SI0 P41/SO0 P42/SCK0 ...
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... Pin MODE0 Note V /MODE1 PP RESET CKSEL SS0 SS1 DD0 DD1 REGOUT µ Note PD70F3114 only 44 CHAPTER 2 PIN FUNCTIONS I/O Circuit Type Recommended Connection 2 − Leave open. − Connect − Connect − Leave open. User’s Manual U15195EJ5V0UD (2/2) − ...
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Pin I/O Circuits Type 2 IN Schmitt-triggered input with hysteresis characteristics Type 4 V Data Output disable Push-pull output with possible high-impedance output (P-ch, N-ch both off) Type Data P-ch Output N-ch disable Input enable CHAPTER ...
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The CPU of the V850E/IA2 is based on RISC architecture and executes almost all instructions in one clock cycle, using 5-stage pipeline control. 3.1 Features • Minimum instruction execution time internal 40 MHz operation) • Memory space ...
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CPU Register Set The registers of the V850E/IA2 can be classified into two categories: a general-purpose program register set and a dedicated system register set. The width of all the registers is 32 bits. For details, refer to V850E1 ...
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Program register set The program register set includes general-purpose registers and a program counter. (1) General-purpose registers Thirty-two general-purpose registers r31, are available. Any of these registers can be used as a data variable or address variable. ...
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... Reserved number for future function expansion (operations that access these register numbers cannot be guaranteed). Notes 1. Because this register has only one set, to allow multiple interrupts necessary to save this register by program. 2. Access is only possible during the period from when the DBTRAP instruction is executed to when the DBRET instruction is executed ...
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Interrupt status saving registers (EIPC, EIPSW) There are two interrupt status saving registers, EIPC and EIPSW. Upon occurrence of a software exception or a maskable interrupt, the contents of the program counter (PC) are saved to EIPC and the ...
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NMI status saving registers (FEPC, FEPSW) There are two NMI status saving registers, FEPC and FEPSW. Upon occurrence of a non-maskable interrupt (NMI), the contents of the program counter (PC) are saved to FEPC and the contents of the ...
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Program status word (PSW) The program status word (PSW collection of flags that indicate the program status (instruction execution result) and the CPU status. When the contents of this register are changed using the LDSR instruction, the ...
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Note During saturated operation, the saturated operation results are determined by the contents of the OV flag and S flag. The SAT flag is set (to 1) only when the OV flag is set (to 1) during saturated operation. Operation ...
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Exception/debug trap status saving registers (DBPC, DBPSW) There are two exception/debug trap status saving registers, DBPC and DBPSW. Upon occurrence of an exception trap or debug trap, the contents of the program counter (PC) are saved to DBPC, and ...
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... ROM, and instruction processing starts. By setting the PMCDH, PMCDL, PMCCT, and PMCCM registers to control mode by instruction, an external device can be connected to the external memory area. (b) ROMless mode After the system reset is cleared, each pin related to the bus interface enters the control mode, program execution branches to the external device’ ...
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Operation mode specification The operation mode is specified according to the status of the MODE0 and MODE1 pins application system, fix the specification of these pins and do not change them during operation. Operation is not guaranteed ...
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Address Space 3.4.1 CPU address space The V850E1 CPU of the V850E/IA2 is of 32-bit architecture and supports linear address space (data space) during operand addressing (data access). Also, in instruction address addressing, a ...
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Image 16 images, each containing a 256 MB physical address space, are seen in the 4 GB CPU address space. In actuality, the same 256 MB physical address space is accessed regardless of the values of bits 31 to ...
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Wrap-around of CPU address space (1) Program space Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. Even if a carry or borrow ...
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Memory map The V850E/IA2 reserves areas as shown in Figure 3-3. Each mode is specified by the MODE0 and MODE1 pins. xFFFFFFFH xFFFF000H xFFFEFFFH xFFFD800H xFFFD7FFH xFFFC000H xFFFBFFFH x0400000H x03FFFFFH x0200000H x01FFFFFH x0100000H x00FFFFFH x0000000H Note By setting the ...
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Area (1) Internal ROM/internal flash memory area (a) Memory map internal ROM/internal flash memory area, addresses 00000H to FFFFFH, is reserved. Actually, internal ROM/internal flash memory of 128 KB is mapped to addresses 000000H to 01FFFFH. ...
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Interrupt/exception table The V850E/IA2 increases the interrupt response speed by assigning handler addresses corresponding to interrupts/exceptions. The collection of these handler addresses is called an interrupt/exception table, which is located in the internal ROM area. When an interrupt/exception request ...
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Internal RAM area memory, addresses FFFC000H to FFFEFFFH, are reserved for the internal RAM area. The 12 KB area of 3FFC000H to 3FFEFFFH can be seen as an image of FFFC000H to FFFEFFFH. In the V850E/IA2, ...
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On-chip peripheral I/O area memory, addresses FFFF000H to FFFFFFFH, are provided as an on-chip peripheral I/O area. An image of addresses FFFF000H to FFFFFFFH can be seen in the area between addresses 3FFF000H and Note 3FFFFFFH ...
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... External memory expansion By setting the port n mode control register (PMCn) to control mode, an external device can be connected to the external memory space using each pin of ports DH, DL, CT, and CM. Each register is set by selecting control mode for each pin of these ports using PMCn (n = DH, DL, CT, CM). ...
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... To enhance the efficiency of using the pointer in connection with of the memory map of the V850E/IA2, the following points are recommended. (1) Program space Of the 32 bits of the program counter (PC), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid ...
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Figure 3-5. Recommended Memory Map Program space FFFFFFFFH FFFFFA78H FFFFFA77H FFFFF000H FFFFEFFFH FFFFD800H FFFFD7FFH FFFFC000H FFFFBFFFH 04000000H 03FFFFFFH On-chip peripheral I/O 03FFF000H 03FFEFFFH Internal RAM 03FFD800H 03FFC7FFH 03FFC000H 03FFBFFFH Program space 64 MB 00400000H 003FFFFFH External memory of V850E/IA2 00100000H ...
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On-chip peripheral I/O registers Address Function Register Name FFFFF004H Port DL FFFFF004H Port DLL FFFFF005H Port DLH FFFFF006H Port DH FFFFF00AH Port CT FFFFF00CH Port CM FFFFF024H Port DL mode register FFFFF024H Port DL mode register L FFFFF025H Port ...
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Address Function Register Name FFFFF09EH DMA destination address register 3H FFFFF0C0H DMA transfer count register 0 FFFFF0C2H DMA transfer count register 1 FFFFF0C4H DMA transfer count register 2 FFFFF0C6H DMA transfer count register 3 FFFFF0D0H DMA addressing control register 0 ...
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Address Function Register Name FFFFF12AH Interrupt control register FFFFF12CH Interrupt control register FFFFF12EH Interrupt control register FFFFF130H Interrupt control register FFFFF13AH Interrupt control register FFFFF13CH Interrupt control register FFFFF13EH Interrupt control register FFFFF140H Interrupt control register FFFFF142H Interrupt control register ...
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Address Function Register Name FFFFF1FEH Power save control register FFFFF200H A/D scan mode register 00 FFFFF200H A/D scan mode register 00L FFFFF201H A/D scan mode register 00H FFFFF202H A/D scan mode register 01 FFFFF202H A/D scan mode register 01L FFFFF203H ...
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Address Function Register Name FFFFF404H Port 2 FFFFF406H Port 3 FFFFF408H Port 4 FFFFF422H Port 1 mode register FFFFF424H Port 2 mode register FFFFF426H Port 3 mode register FFFFF428H Port 4 mode register FFFFF442H Port 1 mode control register FFFFF444H ...
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... FFFFF5EFH Status register 0 FFFFF5F6H CC101 capture input selection register FFFFF5F8H Timer 10 noise elimination time select register NRC10 FFFFF620H Timer connection selection register 0 FFFFF630H Timer 2 input filter mode register 0 FFFFF631H Timer 2 input filter mode register 1 FFFFF632H Timer 2 input filter mode register 2 FFFFF633H ...
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Address Function Register Name FFFFF635H Timer 2 input filter mode register 5 FFFFF640H Timer 2 clock stop register 0 FFFFF640H Timer 2 clock stop register 0L FFFFF641H Timer 2 clock stop register 0H FFFFF642H Timer 2 count clock/control edge selection ...
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Address Function Register Name FFFFF65EH Timer 2 subchannel 4 main capture/compare register FFFFF660H Timer 2 subchannel 0 capture/compare register FFFFF662H Timer 2 subchannel 5 capture/compare register FFFFF664H Timer 2 time base status register 0 FFFFF664H Timer 2 time base status ...
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Address Function Register Name FFFFF882H External interrupt mode register 1 FFFFF884H External interrupt mode register 2 FFFFF8D4H Flash programming mode control register FFFFF900H Clocked serial interface mode register 0 FFFFF901H Clocked serial interface clock selection register 0 FFFFF902H Clocked serial ...
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Address Function Register Name FFFFF920H Prescaler mode register 3 FFFFF922H Prescaler compare register 3 FFFFFA00H Asynchronous serial interface mode register 0 ASIM0 FFFFFA02H Receive buffer register 0 FFFFFA03H Asynchronous serial interface status register 0 FFFFFA04H Transmit buffer register 0 FFFFFA05H ...
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Specific registers Specific registers are registers that are protected from being written with illegal data due to inadvertent program loop (runaway), etc. The V850E/IA2 has three specific registers, the power save control register (PSC) (refer to 8.5.2 (3) Power ...
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Restriction on conflict between sld instruction and interrupt request (a) Description If a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an interrupt request before ...
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... Programmable wait function wait states can be inserted • External wait function via WAIT pin • Idle state insertion function • External device connection enabled via bus control/port alternate function pins 4.2 Bus Control Pins The following pins are used for connection to external devices. ...
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Memory Block Function In the V850E/IA1, the 256 MB memory space is divided into memory blocks and 64 MB units. The programmable wait function and bus cycle operation mode can be independently controlled for each block. ...
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Chip select control function Of the 256 MB memory area, the lower 8 MB (0000000H to 07FFFFFH) and the higher 8 MB (F800000H to FFFFFFFH) can be divided into 2 MB memory blocks by chip area selection control registers ...
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CHAPTER 4 BUS CONTROL FUNCTION CSC0 CS33 CS32 CS31 CS30 CS23 CS22 CS21 CSC1 CS43 CS42 CS41 CS40 CS53 CS52 CS51 Bit position Bit name ...
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The following diagram shows the CS signal that is enabled for area 0 when the CSC0 register is set to 0703H. When the CSC0 register is set to 0703H, CS0 and CS2 are output to block 0 and block 1, ...
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... In the V850E/IA2, the following external devices can be connected directly to each memory block. • SRAM, external ROM, external I/O Connected external devices are specified by bus cycle type configuration registers 0 and 1 (BCT0 and BCT1). (1) Bus cycle type configuration registers 0, 1 (BCT0, BCT1) These registers can be read/written in 16-bit units. ...
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Bus Access 4.5.1 Number of access clocks The number of basic clocks required to access each resource is shown below. Bus Cycle Status Resource (Bus Width) Internal ROM (32 bits) Internal RAM (32 bits) On-chip peripheral I/O (16 bits) ...
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Bus sizing function The bus sizing function controls the data bus width for each CS space. The data bus width is specified by using the bus size configuration register (BSC). (1) Bus size configuration register (BSC) This register can ...
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Bus width The V850E/IA2 accesses on-chip peripheral I/O and external memory in 8-bit, 16-bit, or 32-bit units. The following shows the operation for each type of access. Access all data in order starting from the lower side. (1) Byte ...
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Halfword access (16 bits) (a) When the bus width is 16 bits (little endian) <1> Access to even address (2n) Address Halfword External data data bus (b) ...
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Word access (32 bits) (a) When the bus width is 16 bits (little endian) (1/2) <1> Access to address 4n 1st access Address ...
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CHAPTER 4 BUS CONTROL FUNCTION (a) When the bus width is 16 bits (little endian) (2/2) <3> Access to address 1st access Address ...
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When the data bus width is 8 bits (little endian) (1/2) <1> Access to address 4n 1st access Address Word ...
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When the data bus width is 8 bits (little endian) (2/2) <3> Access to address 1st access Address ...
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Wait Function 4.6.1 Programmable wait function (1) Data wait control registers 0, 1 (DWC0, DWC1) To facilitate interfacing with low-speed memory or with I/Os possible to insert data wait states in the bus cycle ...
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CHAPTER 4 BUS CONTROL FUNCTION (2) Address wait control register (AWC) In the V850E/IA2, address setup wait and address hold wait states can be inserted before and after the T1 cycle, respectively. These wait states can be set for each ...
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... External wait function When an extremely slow device asynchronous system is connected, an arbitrary number of wait states can be inserted in the bus cycle by the external wait pin (WAIT) for synchronization with the external device. Just as with programmable waits, accessing internal ROM, internal RAM, and on-chip peripheral I/O areas cannot be controlled by external waits ...
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Idle State Insertion Function To facilitate interfacing with low-speed memory devices, a set number of idle states (T1) can be inserted into the bus cycle to be activated after the T3 state to secure the data output float delay ...
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Bus Priority Order There are three external bus cycles: DMA cycle, operand data access, and instruction fetch. In order of priority, DMA cycle is the highest, followed by operand data access and instruction fetch, in that order. An instruction ...
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Boundary Operation Conditions 4.9.1 Program space (1) Branching to the on-chip peripheral I/O area or successive fetches from the internal RAM area to the on-chip peripheral I/O area are prohibited. If the above is performed (branching or successive fetch), ...
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CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.1 SRAM, External ROM, External I/O Interface 5.1.1 Features • SRAM is accessed in a minimum of 3 states. • A maximum of 7 programmable data wait states can be inserted according to DWC0 ...
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CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.1.2 SRAM, external ROM, external I/O access Figure 5-1. SRAM, External ROM, External I/O Access Timing (1/4) CLKOUT (output) A16 to A21 (output) AD0 to AD15 (I/O) ASTB (output) RD (output) H UWR, LWR ...
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CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-1. SRAM, External ROM, External I/O Access Timing (2/4) (b) When reading (0 waits, address setup waits, address hold wait states inserted) TASW CLKOUT (output) A16 to A21 (output) AD0 to AD15 (I/O) ...
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CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-1. SRAM, External ROM, External I/O Access Timing (3/4) CLKOUT (output) A16 to A21 (output) Address AD0 to AD15 (I/O) ASTB (output (output) UWR, LWR (output) WAIT (input) Note AD0 to ...
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CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-1. SRAM, External ROM, External I/O Access Timing (4/4) (d) When writing (0 waits inserted, for 8-bit data bus) CLKOUT (output) A16 to A21 (output) AD8 to AD15 (I/O) AD0 to AD7 (I/O) ...
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CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) The V850E/IA2 includes a direct memory access (DMA) controller (DMAC) that executes and controls DMA transfer. The DMAC controls data transfer between memory and peripheral I/O, between memories or between peripheral I/Os, based on ...
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CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.2 Configuration CPU External I/O Remark 106 Internal RAM Internal bus On-chip peripheral I/O bus Data Address control control Count control Channel control Bus interface External bus External External ...
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CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3 Control Registers 6.3.1 DMA source address registers (DSA0 to DSA3) These registers are used to set the DMA source addresses (28 bits each) for DMA channel ...
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CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (2) DMA source address registers (DSA0L to DSA3L) These registers can be read/written in 16-bit units DSA0L SA15 SA14 SA13 SA12 SA11 SA10 15 14 ...
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CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.2 DMA destination address registers (DDA0 to DDA3) These registers are used to set the DMA destination address (28 bits each) for DMA channel 3). They ...
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CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (2) DMA destination address registers (DDA0L to DDA3L) These registers can be read/written in 16-bit units DDA0L DA15 DA14 DA13 DA12 DA11 DA10 15 14 ...
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CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.3 DMA transfer count registers (DBC0 to DBC3) These 16-bit registers are used to set the byte transfer counts for DMA channels 3). They store the ...
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... Be sure to set bits and they are set to 1, the operation is not guaranteed. Cautions 1. The DS1 and DS0 bits are used to set how many bits of data are transferred. When 8-bit data (DS1, DS0 bits = 00) is set, the lower data bus (AD0 to AD7) is not necessarily used. ...
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CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Bit position Bit name 7, 6 SAD1, Sets the count direction of the source address for DMA channel 3). SAD0 SAD1 DAD1, Sets ...
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CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.5 DMA channel control registers (DCHC0 to DCHC3) These 8-bit registers are used to control the DMA transfer operating mode for DMA channel 3). These registers ...
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CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) <7> DCHC0 TC0 0 0 <7> DCHC1 TC1 0 0 <7> DCHC2 TC2 0 0 <7> DCHC3 TC3 0 0 Bit position Bit name 7 TCn ...
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CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.6 DMA disable status register (DDIS) This register holds the contents of the Enn bit of the DCHCn register when DMA is forcibly suspended (during NMI input 3). This register ...
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... No DMA transfer request 1: DMA transfer request If the interrupt specified as the DMA transfer start factor occurs and it is necessary to clear the DMA transfer request while DMA transfer is disabled (including when it is aborted by NMI or forcibly stopped by software), stop the operation that has caused the interrupt (e.g., if serial reception is in progress, by disabling reception) and then clear the DFn bit ...
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CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Bit position Bit name IFCn5 to Sets the interrupt source that serves as the DMA transfer start factor. IFCn0 IFCn5 ...
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CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Bit position Bit name IFCn5 to IFCn0 IFCn5 Other than above Remark ...
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CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.4 Transfer Modes 6.4.1 Single transfer mode In single transfer mode, the DMAC releases the bus at each byte/halfword transfer. If there is a subsequent DMA transfer request, transfer is performed again once. This ...
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CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-3 shows a single transfer mode example in which a lower priority DMA transfer request is generated within one clock after the end of a single transfer. DMA channels 0 and 3 are ...
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CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.4.2 Single-step transfer mode In single-step transfer mode, the DMAC releases the bus at each byte/halfword transfer. Once a DMA transfer request signal has been received, transfer continues until a terminal count occurs. When ...
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CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.4.3 Block transfer mode In the block transfer mode, once transfer starts, the DMAC continues the transfer operation without releasing the bus until a terminal count occurs. No other DMA requests are acknowledged during ...
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CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.6 Transfer Target 6.6.1 Transfer type and transfer target Table 6-1 lists the relationship between the transfer type and transfer target (√: Transfer enabled, ×: Transfer disabled). Table 6-1. Relationship Between Transfer Type and ...
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CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.6.2 External bus cycles during DMA transfer (two-cycle transfer) The external bus cycles during DMA transfer (two-cycle transfer) are shown below. Table 6-2. External Bus Cycles During DMA Transfer (Two-Cycle Transfer) Transfer Target On-chip ...
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CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-8 shows the configuration of the buffer register. Figure 6-8. Buffer Register Configuration Data read Data write The actual DMA transfer is performed based on the settings of the slave register. The settings ...
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... STGn bit was manipulated for the first time therefore necessary to manipulate the STGn bit next time (the second time) after checking whether DMA transfer started by the first manipulation of the STGn bit has been completed ...
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CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.10 Forcible Suspension DMA transfer can be forcibly suspended by NMI input during DMA transfer. At such a time, the DMAC resets the Enn bit of the DCHCn register of all channels to 0 ...
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CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.12 Forcible Termination In addition to the forcible interruption operation by means of NMI input, DMA transfer can be forcibly terminated by the INITn bit of the DCHCn register ( 3). ...
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CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.12.1 Restrictions on forcible termination of DMA transfer During the procedure to forcibly terminate DMA transfer using the INITn bit of the DCHCn register, the transfer may not be terminated and suspended instead even ...
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CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (2) Repetitively setting the INITn bit of the DCHCn register until the transfer is forcibly terminated successfully The preventive processing steps are shown below. <1> Copy the initial transfer count of the channel to ...
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CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.14 Cautions (1) Memory boundary The transfer operation is not guaranteed if the source or the destination address exceeds the area of DMA targets (external memory, internal RAM, or on-chip peripheral I/O) during DMA ...
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CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (7) Read values of DSAn and DDAn registers If the values of the DSAn and DDAn registers are read during DMA transfer, the values in the middle of being updated may be read (n ...
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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION The V850E/IA2 is provided with an interrupt controller (INTC) that can process a total of 48 interrupt requests. An interrupt is an event that occurs independently of program execution, and an exception is an event ...
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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 7-1. Interrupt/Exception Source List (1/2) Type Classification Name Reset Interrupt RESET Non-maskable Interrupt NMI0 Note 1 Software Exception TRAP0n exception Note 1 Exception TRAP1n Exception trap Exception ILGOP/DBG0 Maskable Interrupt INTP0 Interrupt INTP1 Interrupt ...
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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 7-1. Interrupt/Exception Source List (2/2) Type Classification Name Maskable Interrupt INTP30/INTCC30 CC3IC0 Interrupt INTP31/INTCC31 CC3IC1 Interrupt INTCM4 Interrupt INTDMA0 Interrupt INTDMA1 Interrupt INTDMA2 Interrupt INTDMA3 − Interrupt − Interrupt − Interrupt − Interrupt Interrupt ...
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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Remarks 1. Default priority: The priority order when two or more maskable interrupt requests are generated at the same time. The highest priority is 0. Restored PC: The value of the program counter (PC) saved ...
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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.2 Non-Maskable Interrupt A non-maskable interrupt request is acknowledged unconditionally, even when interrupts are in the interrupt disabled (DI) status. An NMI is not subject to priority control and takes precedence over all the other ...
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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.2.1 Operation If a non-maskable interrupt is generated, the CPU performs the following processing, and transfers control to the handler routine. (1) Saves the restored PC to FEPC. (2) Saves the current PSW to FEPSW. ...
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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-2. Acknowledging Non-Maskable Interrupt Request ( new NMI request is generated while an NMI service program is being executed Main routine NMI request ( new NMI request is generated twice ...
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... Caution When the PSW.EP bit and PSW.NP bit are changed by the LDSR instruction during non- maskable interrupt servicing, in order to restore the PC and PSW correctly during recovery by the RETI instruction necessary to set PSW.EP back to 0 and PSW.NP back to 1 using the LDSR instruction immediately before the RETI instruction. ...
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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.2.3 Non-maskable interrupt status flag (NP) The NP flag is a status flag that indicates that non-maskable interrupt (NMI) servicing is under execution. This flag is set when an NMI interrupt has been acknowledged, and ...
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... Note that only interrupts with a higher priority will have this capability; interrupts with the same priority level cannot be nested. However, if multiple interrupts are executed, the following processing is necessary. <1> Save EIPC and EIPSW in memory or a general-purpose register before executing the EI instruction. ...
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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION INTC acknowledged CPU processing Note For details of the ISPR register, see 7.3.6 In-service priority register (ISPR). The INT input masked by the interrupt controllers and the INT input that occurs while another interrupt is ...
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... Caution When the PSW.EP bit and the PSW.NP bit are changed by the LDSR instruction during maskable interrupt servicing, in order to restore the PC and PSW correctly during recovery by the RETI instruction necessary to set PSW.EP back to 0 and PSW.NP back to 0 using the LDSR instruction immediately before the RETI instruction. ...
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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.3 Priorities of maskable interrupts The V850E/IA2 provides multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels. There are two types ...
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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-6. Example of Servicing in Which Another Interrupt Request Is Issued While an Interrupt Is Being Serviced (1/2) Main routine EI Interrupt Interrupt request a request b (level 3) (level 2) Interrupt request c ...
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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-6. Example of Servicing in Which Another Interrupt Request Is Issued While an Interrupt Is Being Serviced (2/2) Main routine EI Interrupt request j Interrupt request i (level 3) (level 2) Interrupt request k ...
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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-7. Example of Servicing Interrupt Requests Generated Simultaneously Main routine EI Interrupt request a (level 2) Interrupt request b (level 1) NMI request Interrupt request c (level 1) Default priority a > b > ...
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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.4 Interrupt control register (xxICn) An interrupt control register is assigned to each interrupt request (maskable interrupt) and sets the control conditions for each maskable interrupt request. This register can be read/written in 8-bit or ...
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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 7-2. Addresses and Bits of Interrupt Control Registers (1/2) Address Register <7> FFFFF110H P0IC0 P0IF0 P0MK0 FFFFF112H P0IC1 P0IF1 P0MK1 FFFFF114H P0IC2 P0IF2 P0MK2 FFFFF116H P0IC3 P0IF3 P0MK3 FFFFF118H P0IC4 P0IF4 P0MK4 − FFFFF11AH ...
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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 7-2. Addresses and Bits of Interrupt Control Registers (2/2) Address Register <7> FFFFF150H CM4IC0 CM4IF0 CM4MK0 FFFFF152H DMAIC0 DMAIF0 DMAMK0 FFFFF154H DMAIC1 DMAIF1 DMAMK1 FFFFF156H DMAIC2 DMAIF2 DMAMK2 FFFFF158H DMAIC3 DMAIF3 DMAMK3 − FFFFF15AH ...
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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.5 Interrupt mask registers (IMR0 to IMR3) These registers set the interrupt mask state for the maskable interrupts. The xxMKn bit of the IMR0 to IMR3 registers is equivalent to the xxMKn ...
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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.6 In-service priority register (ISPR) This register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt request is acknowledged, the bit of this register corresponding to the priority level of that ...
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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.7 Maskable interrupt status flag (ID) The ID flag is bit 5 of the PSW and this controls the maskable interrupt’s operating state, and stores control information regarding enabling or disabling of interrupt requests. 31 ...
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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (1) External interrupt mode registers 1, 2 (INTM1, INTM2) These registers specify the valid edge for external interrupt requests (INTP0 to INTP4), input via external pins. The correspondence between each register and the external interrupt ...
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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) Signal edge selection register 10 (SESA10) These registers specify the valid edge of external interrupt requests (INTP100, INTP101, TIUD10, TCUD10, and TCLR10), input via external pins. The valid edge can be specified independently for ...
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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Bit position Bit name 5, 4 CESUD01, Specifies the valid edge of the TLCR10 pin CESUD00 The setting values of the CESUD01 and CESUD00 bits and the operation of TM10 are as follows. Caution 3, ...
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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (3) Valid edge selection register (SESC) This register specifies the valid edge for external interrupt requests (INTP30, INTP31, TCLR3, TI3), input via external pins. The valid edge can be specified independently for each pin (rising ...
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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (4) Timer 2 input filter mode registers (FEM0 to FEM5) These registers specify the valid edge for external interrupts input to timer 2 (INTP20 to INTP25). correspondence between each register and the ...
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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION FEM0 DFEN00 FEM1 DFEN01 FEM2 DFEN02 FEM3 DFEN03 FEM4 DFEN04 0 0 ...
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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Bit position Bit name 1, 0 TMS01n, Selects the capture input TMS00n Note Selection of capture input based on INTCM100 and INTCM101 is valid only for the FEM1 and FEM2 registers. Set the TMS01m and ...
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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.4 Software Exception A software exception is generated when the CPU executes the TRAP instruction, and can be always acknowledged. 7.4.1 Operation If a software exception occurs, the CPU performs the following processing, and transfers ...
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... Caution When the PSW.EP bit and the PSW.NP bit are changed by the LDSR instruction during the software exception processing, in order to restore the PC and PSW correctly during recovery by the RETI instruction necessary to set PSW.EP back to 1 using the LDSR instruction immediately before the RETI instruction. ...
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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.4.3 Exception status flag (EP) The EP flag is bit 6 of PSW, and is a status flag used to indicate that exception processing is in progress set when an exception occurs. 31 ...
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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.5 Exception Trap An exception trap is an interrupt that is requested when an illegal execution of an instruction takes place. In the V850E/IA2, an illegal opcode exception (ILGOP: Illegal Opcode Trap) is considered as ...
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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-10. Exception Trap Processing CPU processing (2) Restore Returning from exception trap processing is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls ...
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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.5.2 Debug trap The debug trap is an exception that can be acknowledged every time and is generated by execution of the DBTRAP instruction. When the debug trap is generated, the CPU performs the following ...
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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) Restore Returning from debug trap processing is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored PC. (1) ...
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... Maskable interrupt multiple processing control is executed when interrupts are enabled (ID = 0). Thus, if multiple interrupts are executed necessary for interrupts to be enabled ( even during an interrupt servicing routine maskable interrupt or a software exception is generated in a maskable interrupt or software exception service program necessary to save EIPC and EIPSW ...
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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) Generation of exception in service program Service program of maskable interrupt or exception ... ... • EIPC saved to memory or register • EIPSW saved to memory or register ... • TRAP instruction ... ...
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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.7 Interrupt Response Time The following table describes the V850E/IA2 interrupt response time (from interrupt generation to start of interrupt servicing). Figure 7-14. Pipeline Operation at Interrupt Request Acknowledgment (Outline) Internal clock Interrupt request Instruction ...
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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.8 Periods in Which CPU Does Not Acknowledge Interrupts The CPU acknowledges an interrupt while an instruction is being executed. acknowledged between an interrupt non-sample instruction and the next instruction (interrupt is held pending). The ...
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... The clock generator (CG) generates and controls the internal system clock (f unit, such as the CPU. 8.1 Features • Multiplier function using a phase locked loop (PLL) synthesizer • Clock sources • Oscillation by connecting a resonator • External clock • Power-saving modes • HALT mode • IDLE mode • ...
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... Caution In direct mode, an external clock must be input (an external resonator should not be connected). 8.3.2 PLL mode In PLL mode, an external resonator is connected or external clock is input and multiplied by the PLL synthesizer. The multiplied PLL output is divided by the division ratio specified by the clock control register (CKC) to generate a system clock that is 10 times the frequency (f After reset, an internal system clock (f generated ...
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CHAPTER 8 CLOCK GENERATION FUNCTION value for which 10 × f Caution Only MHz) (i.e. 4 MHz) can be used for the oscillation frequency or external clock frequency. When 5 × 2.5 × ...
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... For details, see 8.6.2 Time base counter (TBC). Specifies the functions of the X1 and X2 pins resonator is connected to the X1 and X2 pins 1: An external clock is connected to the X1 pin When CESEL = 1, the oscillator feedback loop is disconnected to prevent current leakage in software STOP mode. Sets the internal system clock frequency (f CKDIV2 CKDIV1 CKDIV0 ...
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CHAPTER 8 CLOCK GENERATION FUNCTION Data is set in the clock control register (CKC) according to the following sequence. <1> Disable interrupts (set the NP bit of PSW to 1) <2> Prepare data in any one of the general-purpose registers ...
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CHAPTER 8 CLOCK GENERATION FUNCTION 8.3.5 Peripheral status register (PHS write operation is not performed in the correct sequence including access to the command register for the protection-targeted internal registers, writing is not performed and a protection error ...
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CHAPTER 8 CLOCK GENERATION FUNCTION 8.4 PLL Lockup The lockup time (frequency stabilization time) is the time from when the power is turned on or the software STOP mode is released until the phase locks at the prescribed frequency. The ...
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... Also, PLL lockup time may be required depending on the program. When a resonator or external clock is connected, following the release of the software STOP mode, execution of the program is started after the count time of the time base counter has elapsed. ...
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CHAPTER 8 CLOCK GENERATION FUNCTION Figure 8-1 shows the operation of the clock generator in normal operation mode, HALT mode, IDLE mode, and software STOP mode. An effective low power consumption system can be realized by combining these modes and ...
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CHAPTER 8 CLOCK GENERATION FUNCTION Table 8-1. Clock Generator Operation Using Power Save Control Clock Source PLL mode Oscillation with resonator External clock Direct mode External clock √: Operating Remark −: Stopped Power Save Mode Oscillator √ Normal operation √ ...
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CHAPTER 8 CLOCK GENERATION FUNCTION 8.5.2 Control registers (1) Power save mode register (PSMR) This is an 8-bit register that controls the power save mode effective only when the STB bit of the PSC register is set to ...
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CHAPTER 8 CLOCK GENERATION FUNCTION (3) Power save control register (PSC) This is an 8-bit register that controls the power save function. If releasing of interrupts are enabled by the setting of the NMIM and INTM bits, the software STOP ...
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CHAPTER 8 CLOCK GENERATION FUNCTION [Sample coding] <1> ST.B <2> MOV <3> ST.B <4> ST.B <5> NOP <6> NOP <7> NOP <8> NOP <9> NOP (next instruction) No special sequence is required to read the specific register. Cautions 1. Interrupts ...
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CHAPTER 8 CLOCK GENERATION FUNCTION 8.5.3 HALT mode (1) Setting and operation status In the HALT mode, the clock generator (oscillator and PLL synthesizer) continues to operate, but the operation clock of the CPU is stopped. Since the supply of ...
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CHAPTER 8 CLOCK GENERATION FUNCTION (2) Release of HALT mode HALT mode is released by a non-maskable interrupt request, an unmasked maskable interrupt request, or RESET pin input. (a) Release by a non-maskable interrupt request or an unmasked maskable interrupt ...
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CHAPTER 8 CLOCK GENERATION FUNCTION 8.5.4 IDLE mode (1) Setting and operation status In the IDLE mode, the clock generator (oscillator and PLL synthesizer) continues to operate, but the supply of internal system clocks is stopped which causes the overall ...
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CHAPTER 8 CLOCK GENERATION FUNCTION (2) Release of IDLE mode IDLE mode is released by a non-maskable interrupt request, an unmasked maskable interrupt request Note (INTPn RESET pin input ( 25). Note ...
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... CLR1, or NOT1 instruction) to set the PSC and PSMR registers (see 8.5.2 Control registers). When PLL mode and resonator connection mode (CESEL bit of CKC register = 1) are used, the oscillator's oscillation stabilization time must be secured after software STOP mode is released. In both PLL and direct mode, following the release of software STOP mode, execution of the program is started after the count time of the time base counter has elapsed ...
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... RESET pin input. Also, to release software STOP mode when PLL mode (CKSEL pin = low level) and resonator connection mode (CESEL bit of CKC register = 0) are used, the oscillator’s oscillation stabilization time must be secured ( 25) Moreover, the oscillation stabilization time must be secured even when an external clock is connected (CESEL bit = 1) ...
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... If the direct mode or external clock connection mode (CESEL bit of CKC register = 1) is used, program execution begins after the count time of the time base counter has elapsed. Also, even if the PLL mode and resonator connection mode (CESEL bit of CKC register = 0) are used, program execution begins after the oscillation stabilization time is secured by the time base counter. ...
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... The time base counter (TBC) is used to secure the oscillator’s oscillation stabilization time when software STOP mode is released. When an external clock is connected (CESEL bit of CKC register = resonator is connected (PLL mode and CESEL bit of CKC register = 0), the TBC counts the oscillation stabilization time after software STOP mode is released, and program execution begins after the count is completed ...
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CHAPTER 9 TIMER/COUNTER FUNCTION 9.1 Timer 0 9.1.1 Features (timer 0) Timers 00 and 01 (TM00, TM01) are 16-bit timer/counters ideal for controlling high-speed inverters such as motors. • 3-phase PWM output function PWM mode 0 (symmetric triangular wave) PWM ...
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Function overview (timer 0) • 16-bit timer (TM0n) for 3-phase PWM inverter control: 2 channels • Compare registers: 6 registers × 2 channels • 12-bit dead-time timers (DTMn0 to DTMn2): 3 timers × 2 channels • Count clock division ...
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Functions added to V850E/IA2 (1) Addition of BFCMn4 and CM0n4 registers, and BFCMn5 and CM0n5 registers When the TM0CEn bit of the TMC0n register is 1 (counting enabled), transferring data from the BFCMn4 or BFCMn5 register to the CM0n4 ...
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Basic configuration The basic configuration is shown below. Figure 9-1. Block Diagram of Timer 0 (Mode 0: Symmetric Triangular Wave, Mode 1: Asymmetric Triangular Wave) BFCMn3 INTCM0n3 CM0n3 1 1/2 XX INTTM0n TM0n 1 ...
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CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-2. Block Diagram of Timer 0 (Mode 2: Sawtooth Wave) BFCMn3 INTCM0n3 CM0n3 1/1 16 Clear f 1/2 XX 1/4 TM0n CLK 1/8 XX 1/16 1/32 16 BFCMn0 CM0n0 INTCM010 BFCMn1 CM0n1 ...
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Timers 00, 01 (TM00, TM01) TM0n operates as a 16-bit up/down timer or up timer. The cycle is controlled by compare register 0n3 (CM0n3 1). TM0n start/stop is controlled by the TM0CEn bit of timer control ...