MBM29F040C-90PD Fujitsu, MBM29F040C-90PD Datasheet

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MBM29F040C-90PD

Manufacturer Part Number
MBM29F040C-90PD
Description
MBM29F040C-90PDFujitsu Media Devices Limited [4M (512K X 8) BIT]
Manufacturer
Fujitsu
Datasheet

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FUJITSU SEMICONDUCTOR
FLASH MEMORY
CMOS
4M (512K
MBM29F040C
Embedded Erase™, Embedded Program™ and ExpressFlash™ are trademarks of Advanced Micro Devices, Inc.
FEATURES
Single 5.0 V read, program and erase
Minimizes system level power requirements
Compatible with JEDEC-standard commands
Uses same software commands as E
Compatible with JEDEC-standard byte-wide pinouts
32-pin PLCC (Package suffix: PD)
32-pin TSOP(I) (Package suffix: PF)
32-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)
Minimum 100,000 write/erase cycles
High performance
55 ns maximum access time
Sector erase architecture
8 equal size sectors of 64K bytes each
Any combination of sectors can be concurrently erased. Also supports full chip erase.
Embedded Erase™ Algorithms
Automatically pre-programs and erases the chip or any sector
Embedded Program™ Algorithms
Automatically writes and verifies data at specified address
Data Polling and Toggle Bit feature for detection of program or erase cycle completion
Low V
Sector protection
Hardware method disables any combination of sectors from write or erase operations
Erase Suspend/Resume
Suspends the erase operation to allow a read data in another sector within the same device
DATA SHEET
CC
write inhibit
3.2 V
-55/-70/-90
2
PROMs
8) BIT
DS05-20842-4E

Related parts for MBM29F040C-90PD

MBM29F040C-90PD Summary of contents

Page 1

... FUJITSU SEMICONDUCTOR DATA SHEET FLASH MEMORY CMOS 4M (512K MBM29F040C FEATURES • Single 5.0 V read, program and erase Minimizes system level power requirements • Compatible with JEDEC-standard commands Uses same software commands as E • Compatible with JEDEC-standard byte-wide pinouts 32-pin PLCC (Package suffix: PD) 32-pin TSOP(I) (Package suffix: PF) 32-pin TSOP(I) (Package suffix: PFTN – ...

Page 2

... MBM29F040C -55/-70/-90 PACKAGE 32-pin Plastic TSOP (I) Marking Side (FPT-32P-M24 — Assembly: Malaysia) 2 32-pin Plastic QFJ (PLCC) Marking Side (LCC-32P-M02) 32-pin Plastic TSOP (I) Marking Side (FPT-32P-M25 — Assembly: Malaysia) ...

Page 3

... GENERAL DESCRIPTION The MBM29F040C is a 4M-bit, 5.0 V-only Flash memory organized as 512K bytes of 8 bits each. The MBM29F040C is offered in a 32-pin PLCC and 32-pin TSOP(I) package. This device is designed to be programmed in-system with the standard system 5 operations. The device can also be reprogrammed in standard EPROM programmers. ...

Page 4

... MBM29F040C -55/-70/-90 FLEXIBLE SECTOR-ERASE ARCHITECTURE • 64K Byte per sector • Individual-sector, multiple-sector, or bulk-erase capability • Individual or multiple-sector protection is user definable 4 7FFFFH 6FFFFH 5FFFFH 64K byte per sector 4FFFFH 3FFFFH 2FFFFH 1FFFFH 0FFFFH 00000H ...

Page 5

... Max. OE Access Time (ns) BLOCK DIAGRAM State Control Command Register CE OE Low V Detector MBM29F040C MBM29F040C -55 — - Erase Voltage Generator Program Voltage Generator Chip Enable Output Enable Logic Y-Decoder STB Timer for Address Program/Erase Latch X-Decoder -55/-70/-90 — ...

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... PLCC LCC-32P-M02 TSOP (I) Marking Side MBM29F040C Standard Pinout FPT-32P-M24 Marking Side MBM29F040C Reverse Pinout FPT-32P-M25 ...

Page 7

... Refer to the section on Sector Protection can MBM29F040C Table 1 MBM29F040C Pin Configuration Pin MBM29F040C User Bus Operations ...

Page 8

... MBM29F040C -55/-70/-90 ORDERING INFORMATION Standard Products Fujitsu standard products are available in several packages. The order number is formed by a combination of: MBM29F040 C -55 DEVICE NUMBER/DESCRIPTION MBM29F040 4Mega-bit (512K 5.0 V-only Read, Program, and Erase 64K Byte Sectors 8 PD PACKAGE TYPE PD =32-Pin Rectangular Plastic Leaded Chip ...

Page 9

... FUNCTIONAL DESCRIPTION Read Mode The MBM29F040C has two control functions which must be satisfied in order to obtain data at the outputs the power control and should be used for a device selection the output control and should be used to gate data to the output pins if a device is selected. ...

Page 10

... Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters. Sector Protection The MBM29F040C features hardware sector protection. This feature will disable both program and erase operations in any number of sectors (0 through 8). The sector protection feature is enabled using programming equipment at the user’s site. The device is shipped with all sectors unprotected. ...

Page 11

... Reset Commands are functionally equivalent, resetting the device to the read mode. MBM29F040C . Scanning the sector addresses (A IH for a protected sector. Otherwise the device will read 0 for a protected sector. See Table 3 for Autoselect codes. 0 MBM29F040C Command Definitions Fourth Bus Second Bus Third Bus Read/Write Write Cycle Write Cycle Cycle — ...

Page 12

... MBM29F040C -55/-70/-90 Read/Reset Command The read or reset operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the command register contents are altered. The device will automatically power-up in the read/reset state. In this case, a command sequence is not required to read data ...

Page 13

... Erase Suspend and Erase Resume commands are allowed. All other commands will reset the device to read mode. Data polling must be performed at an address within any of the sectors being erased. Figure 14 illustrates the Embedded Erase MBM29F040C 3 , Sector Erase Timer.) Any command other than Sector Erase “ ...

Page 14

... MBM29F040C -55/-70/-90 Erase Suspend The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase operation which include the time-out period for sector erase. The Erase Suspend command will be ignored if written during the Chip Erase operation or Embedded Program Algorithm ...

Page 15

... DQ 7 Data Polling The MBM29F040C device features Data Polling as a method to indicate to the host that the Embedded Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the device will produce the compliment of the data last written read the device will produce the true data last written to DQ attempt to read the device will produce a “ ...

Page 16

... DQ 6 Toggle Bit I The MBM29F040C also features the “Toggle Bit I” method to indicate to the host system that the Embedded Algorithms are in progress or completed. During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the device will result in DQ toggling between one and zero ...

Page 17

... These status flags apply when outputs are read from the byte address of the non-erase suspended sector. Data Protection The MBM29F040C is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the device automatically resets the internal state machine in the Read mode ...

Page 18

... MBM29F040C -55/-70/-90 Power-Up Write Inhibit Power-up of the device with The internal state machine is automatically reset to the read mode on power-up. 18 and will not accept commands on the rising edge of WE ...

Page 19

... Supply Voltages CC MBM29F040C-55.......................................................................................... +4. +5.25 V MBM29F040C-70/-90 ................................................................................... +4. +5.50 V Operating ranges define those limits between which the functionality of the device is guaranteed. WARNING: The recommended operating conditions are required in order to ensure normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges ...

Page 20

... MBM29F040C -55/-70/-90 MAXIMUM OVERSHOOT +0.8 V –0.5 V –2.0 V Figure +2.0 V Figure 2 +14.0 V +13 +0 This waveform is applied for A Figure Maximum Negative Overshoot Waveform Maximum Positive Overshoot Waveform OE. 9 Maximum Positive Overshoot Waveform 2 ...

Page 21

... DC operating current and the frequency dependent component CC (at 6 MHz). The frequency component typically is 2 mA/MHz, with active while Embedded Algorithm (program or erase progress Applicable to sector protection function – not exceed MBM29F040C Test Conditions Max ...

Page 22

... MBM29F040C -55/-70/-90 AC CHARACTERISTICS • Read Only Operations Characteristics Parameter Symbols JEDEC Standard t t Read Cycle Time AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ELQV Output Enable to Output Delay GLQV Chip Enable to Output HIGH-Z EHQZ ...

Page 23

... Min. Min. Read Min. Toggle and Data Polling Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Typ. Typ. Max. Min. Min. Min. Min. Min. Max. -55/-70/-90 MBM29F040C Unit -55 -70 - ...

Page 24

... MBM29F040C -55/-70/-90 SWITCHING WAVEFORMS • Key to Switching Waveforms Addresses High-Z Outputs Figure 5 24 WAVEFORM INPUTS OUTPUTS Must Be Will Be Steady Steady May Will Be Change Changing from from May Will Be Change Changing from from “H” or “L” Changing ...

Page 25

... D is the output of the data written to the device. OUT 5. Figure indicates last two bus cycles of four bus cycle sequence. Figure 6 AC Waveforms for Alternate WE Controlled Program Operations MBM29F040C Data Polling PA t WHWH1 ...

Page 26

... MBM29F040C -55/-70/-90 3rd Bus Cycle Addresses Data 5.0V Notes address of the memory location to be programmed data to be programmed at byte address the output of the complement of the data written to the device the output of the data written to the device. OUT 5 ...

Page 27

... GHWL WPH t DH Data AAH VCS * : SA is the sector address for Sector Erase. Addresses = 555H for Chip Erase Figure 8 AC Waveforms Chip/Sector Erase Operations MBM29F040C t AH 2AAH 555H 555H 2AAH t AS 55H 80H AAH -55/-70/- 55H 10H/30H 27 ...

Page 28

... MBM29F040C -55/-70/- Data Data Valid Data (The device has completed the Embedded operation.) 7 Figure 9 AC Waveforms for Data Polling during Embedded Algorithm Operations OES OE Data stops toggling (The device has completed the Embedded operation). ...

Page 29

... VLHT VLHT WE t OESP t CSP CE Data t VCS V CC SAX : Sector Address for initial sector SAY : Sector Address for next sector Figure 11 AC Waveforms for Sector Protection Timing Diagram MBM29F040C t t VLHT VLHT t WPP t OE -55/-70/-90 SAY 01H 29 ...

Page 30

... MBM29F040C -55/-70/-90 Enter Erase Embedded Suspend Erasing WE Erase Erase Suspend Toggle DQ and with OE Note read from the erase-suspended sector Enter Erase Suspend Program Erase Erase Suspend Read Suspend Read Program Figure Erase Resume Erase ...

Page 31

... EMBEDDED ALGORITHMS Increment Address Figure 13 MBM29F040C Start Write Program Command Sequence (See below) Data Polling Device No Last Address ? Yes Programming Completed Program Command Sequence (Address/Command) 555H/AAH 2AAH/55H 555H/A0H Program Address/Program Data Embedded Program TM Algorithm -55/-70/-90 31 ...

Page 32

... MBM29F040C -55/-70/-90 EMBEDDED ALGORITHMS Chip Erase Command Sequence (Address/Command): 555H/AAH 2AAH/55H 555H/80H 555H/AAH 2AAH/55H 555H/10H 32 Start Write Erase Command Sequece (See below) Data Polling or Toggle Bit Successfully Completed Erasure Completed Individual Sector/Multiple Sector Erase Command Sequence (Address/Command): 555H/AAH 2AAH/55H 555H/80H 555H/AAH 2AAH/55H ...

Page 33

... Addr Read Byte (DQ Addr Note rechecked even Figure 5 MBM29F040C Start VA = Byte address for programming Any of the sector addresses within the sector being erased during sector erase or multiple sector Yes erases operation. = Data ...

Page 34

... MBM29F040C -55/-70/-90 Note rechecked even changing to “1”. 34 Start Read Byte ( Addr. = “H” or “L” Toggle 6 ? Yes Yes Read Byte ( Addr. = “H” or “L” Toggle 6 ? Yes Fail Pass = “1” because DQ ...

Page 35

... V 9 Read from Sector Addr PLSCNT = 25? Yes Remove V from A Protect Another Sector ? ID 9 Write Reset Command Remove V Device Failed Write Reset Command Sector Protection Figure 7 Sector Protection Algorithm MBM29F040C -55/-70/-90 Start ( PLSCNT = ...

Page 36

... MBM29F040C -55/-70/-90 ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Byte Programming Time Chip Programming Time Erase/Program Cycle TSOP(I) PIN CAPACITANCE Parameter Parameter Description Symbol C Input Capacitance IN C Output Capacitance OUT C Control Pin Capacitance IN2 Note: Test conditions T = 25° 1.0 MHz A PLCC PIN CAPACITANCE ...

Page 37

... TYP +0.05 0.20 –0.02 +.002 .008 –.001 0.43(.017) 0.10(.004) TYP 10.41±0.51 (.410±.020) 1994 FUJITSU LIMITED C32021S-2C-4 C MBM29F040C 3.40±0.16 (.134±.006) 2.25±0.38 (.089±.015) 0.64(.025) MIN 14.94±0.13 12.95±0.51 (.588±.005) (.510±.020) R0.95(.037) TYP -55/-70/-90 7.62(.300)REF 1.27±0.13 (.050± ...

Page 38

... MBM29F040C -55/-70/-90 32-pin plastic TSOP(I) (FPT-32P-M24) LEAD No. 1 INDEX 16 0.15±0.05 (.006±.002) 20.00±0.20 (.787±.008) 18.40±0.20 (.724±.008) 19.00±0.20 (.748±.008) 1994 FUJITSU LIMITED F32035S-2C Details of "A" part 32 "A" 17 0.50(.0197) TYP 0.10(.004) 0.50±0.10 (.020±.004) ...

Page 39

... INDEX 16 19.00±0.20 (.748±.008) 0.15±0.05 (.006±.002) 0.10(.004) 18.40±0.20 (.724±.008) 20.00±0.20 (.787±.008) 1997 FUJITSU LIMITED F32036S-2C-2 C MBM29F040C Details of "A" part 32 "A" 17 0.15(.006) 0.25(.010) 0.20±0.10 0.10(.004) (.008±.004) 0.50±0.10 7.50(.295) (.020±.004) REF ...

Page 40

... MBM29F040C -55/-70/-90 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division ...

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