AS3842 Astec Power, AS3842 Datasheet

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AS3842

Manufacturer Part Number
AS3842
Description
Switching power supply control
Manufacturer
Astec Power
Datasheet

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SWITCHING POWER SUPPLY CONTROL
LOOP DESIGN
© ASTEC Semiconductor
Mike Wong
1. Introduction
In a switched mode power converter, the con-
duction time of the power switch is regulated
according to the input and output voltages. Thus,
a power converter is a self-contained control
system in which the conduction time is modu-
lated in reaction to changes in the input and
output voltages. From a theoretical approach,
control loop design often involves complicated
equations, making control a challenging but
often misunderstood area in switched mode
power supply design. A simplified approach to
feedback control loop analysis is presented in
the following pages, beginning with a general
overview of various parameters affecting per-
formance in a switching power system. A dem-
onstration of an actual power supply is given to
show the components involved in designing the
characteristics of the control loop. Test results
and measurement techniques are also included.
V
IN
f
T(S) =
POLE
R
=
V
V
OUT (S)
IN (S)
2 RC
1
=
C
RCs + 1
1
V
OUT
PHASE
Figure 1.
GAIN
– 45°
–90°
0dB
161
2. Basic Control Loop Concepts
2.1 Transfer Functions and the Bode Plots
The transfer function of a system is defined as
the output divided by the input. It consists of a
gain and a phase element that can be plotted
separately in a Bode plot. The gain around a
closed loop system is the product of the gains of
all the elements around the loop. In a Bode plot,
the gain is plotted logarithmically. Since the
product of two numbers is their logarithmic sum,
their gains can be summed graphically. The
phase of the system is the sum of all phase shifts
around the loop.
2.2 Poles
Mathematically, in a transfer equation, a pole
occurs when its denominator becomes zero.
Graphically, a pole in the bode plot occurs when
the slope of the gain decreases by 20 dB per
decade. Figure 1 illustrates a low pass filter
commonly used for creating a pole in the sys-
tem. Its transfer function and Bode plots are
also shown.
Application Note 5
f
f
POLE
POLE
AS3842

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AS3842 Summary of contents

Page 1

... Figure 1 illustrates a low pass filter commonly used for creating a pole in the sys- tem. Its transfer function and Bode plots are also shown. GAIN 0dB V OUT PHASE 0° – 45° –90° Figure 1. 161 AS3842 Application Note 5 f POLE f POLE ...

Page 2

... AS3842 – (S) –1 OUT T( ( R1Cs ZERO 2 R2C 2.3 Zeros A zero in a frequency domain transfer function occurs when the numerator of the equation goes to zero Bode plot, a zero occurs at a point where the slope of the gain increases per decade accompanied by 90 phase lead ...

Page 3

... PWM circuit, error amplifier compensation, and feedback . Figure 5 illustrates a block diagram of the four stages and Figure 6 illustrates a power supply circuit diagram. 163 AS3842 PHASE MARGIN ...

Page 4

... REG SENSE OUT R12 R C GND T T AS3842 C9 C8 R10 PWM CIRCUIT (G2) ASTEC Semiconductor 4.1 Feedback Network, H(s): The feedback network divides the output volt- G1 (S) age down to the reference level of the error V OUT amplifier. Its transfer equation is simply a resis- tor divider equation: H (S) 4 ...

Page 5

... CTR is the current transfer ratio of the optocoupler the current limit resistor in series with the optocoupler diode. R output impedance of the AS3842 Comp pin when it tries to source above its maximum output current. After the error signal is transferred to the com- pensation pin compared with a current sense signal ...

Page 6

... AS3842 N COMP I – SENSE R I SENSE PRIMARY Figure 9. Since I , the secondary current or out- SECONDARY put current, is proportional to the primary cur- rent, equation (4) can be rearranged to show a relationship between secondary current and V . COMP – REF R1C2 ERROR G3( (C2 + C1) + SR1 (C2 C1) ...

Page 7

... Figure 12 shows its gain-phase plot. As predicted by Figure 11, the same Bode plot curvature was acquired. The gain-phase shows the system has a phase margin 167 AS3842 F CS PHASE MARGIN ...

Page 8

... AS3842 of 86.7 , implying a stable system with a fast transient response. Figure 13 shows the transient response of the system. To demonstrate the effects of phase margin, the phase margin of the system was decreased by increasing the overall gain of the system, increasing the crossover fre- quency. The phase margin decreases with in- creasing crossover frequency ...

Page 9

... input of the AS3842. The input impedance is the impedance looking into the V output impedance is the output impedance of the optocoupler. In other applications where the error amplifier can not be separated from the ...

Page 10

... AS3842 Notes ASTEC Semiconductor Application Note 5 170 ...

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