MC68030RC33

Manufacturer Part NumberMC68030RC33
DescriptionMC68030RC33ENHANCED 32-BIT MICROPROCESSOR
ManufacturerMotorola
MC68030RC33 datasheet
 
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On-Chip Cache Memories
6.1 ON-CHIP CACHE ORGANIZATION AND OPERATION
Both on-chip caches are 256-byte direct-mapped caches, each organized as 16 lines. Each
line consists of four entries, and each entry contains four bytes. The tag field for each line
contains a valid bit for each entry in the line; each entry is independently replaceable. When
appropriate, the bus controller requests a burst mode operation to replace an entire cache
line. The cache control register (CACR) is accessible by supervisor programs to control the
operation of both caches.
System hardware can assert the cache disable (CDIS) signal to disable both caches. The
assertion of CDIS disables the caches, regardless of the state of the enable bits in CACR.
CDIS is primarily intended for use by in-circuit emulators.
Another input signal, cache inhibit in (CIIN), inhibits caching of data reads or instruction
prefetches on a bus-cycle by bus-cycle basis. Examples of data that should not be cached
are data for I/O devices and data from memory devices that cannot supply a full port width
of data, regardless of the size of the required operand.
Subsequent paragraphs describe how CIIN is used during the filling of the caches.
An output signal, cache inhibit out (CIOUT), reflects the state of the cache inhibit (CI) bit from
the MMU of either the address translation cache entry that corresponds to a specified logical
address or the transparent translation register that corresponds to that address. Whenever
the appropriate CI bit is set for either a read or a write access and an external bus cycle is
required, CIOUT is asserted and the instruction and data caches are ignored for the access.
This signal can also be used by external hardware to inhibit caching in external caches.
Whenever a read access occurs and the required instruction word or data operand is
resident in the appropriate on-chip cache (no external bus cycle is required), the MMU is
completely ignored, unless an invalid translation resides in the MMU at that time (see next
two paragraphs). Therefore, the state of the corresponding CI bits in the MMU are also
ignored. The MMU is used to validate all accesses that require external bus cycles; an
address translation must be available and valid, protections are checked, and the CIOUT
signal is asserted appropriately.
MOTOROLA
MC68030 USER’S MANUAL
6-3