MC68030RC33

Manufacturer Part NumberMC68030RC33
DescriptionMC68030RC33ENHANCED 32-BIT MICROPROCESSOR
ManufacturerMotorola
MC68030RC33 datasheet
 


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
Page 141
142
Page 142
143
Page 143
144
Page 144
145
Page 145
146
Page 146
147
Page 147
148
Page 148
149
Page 149
150
Page 150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
Page 141/602

Download datasheet (4Mb)Embed
PrevNext
On-Chip Cache Memories
the read cycle in error is made only to fill the data cache (the data is not part of the target
operand), no exception occurs, but the corresponding entry is marked invalid. For the
instruction cache, the processor marks the entry as invalid, but only takes an exception if
the execution unit attempts to use the instruction word(s).
6.1.3.2 BURST MODE FILLING. Burst mode filling is enabled by bits in the cache control
register. The data burst enable bit must be set to enable burst filling of the data cache.
Similarly, the instruction burst enable bit must be set to enable burst filling of the instruction
cache. When burst filling is enabled and the corresponding cache is enabled, the bus
controller requests a burst mode fill operation in either of these cases:
• A read cycle for either the instruction or data cache misses due to the indexed tag not
matching.
• A read cycle tag matches, but all long words in the line are invalid.
The bus controller requests a burst mode fill operation by asserting the cache burst request
signal (CBREQ). The responding device may sequentially supply one to four long words of
cachable data, or it may assert the cache inhibit input signal (CIIN) when the data in a long
word is not cachable. If the responding device does not support the burst mode and it
terminates cycles with STERM, it should not acknowledge the request with the assertion of
the cache burst acknowledge (CBACK) signal. The MC68030 ignores the assertion of
CBACK during cycles terminated with DSACKx.
The cache burst request signal (CBREQ) requests burst mode operation from the
referenced external device. To operate in the burst mode, the device or external hardware
must be able to increment the low-order address bits if required, and the current cycle must
be a 32-bit synchronous transfer (STERM must be asserted) as described in Section 7 Bus
Operation . The device must also assert CBACK (at the same time as STERM) at the end
of the cycle in which the MC68030 asserts CBREQ. CBACK causes the processor to
continue driving the address and bus control signals and to latch a new data value for the
next cache entry at the completion of each subsequent cycle (as defined by STERM), for a
total of up to four cycles (until four long words have been read).
When a cache burst is initiated, the first cycle attempts to load the cache entry
corresponding to the instruction word or data item explicitly requested by the execution unit.
The subsequent cycles are for the subsequent entries in the cache line. In the case of a
misaligned transfer when the operand spans two cache entries within a cache line, the first
cycle corresponds to the cache entry containing the portion of the operand at the lower
address.
Figure 6-11 illustrates the four cycles of a burst operation and shows that the second, third,
and fourth cycles are run in burst mode. A distinction is made between the first cycle of a
burst operation and the subsequent cycles because the first cycle is requested by the
microsequencer and the burst fill cycles are requested by the bus controller. Therefore,
when data from the first cycle is returned, it is immediately available for the execution unit
(EU). However, data from the burst fill cycles is not available to the EU until the burst
operation is complete. Since the microsequencer makes two separate requests for
misaligned data operands, only the first portion of the misaligned operand returned during a
6-12
MC68030 USER’S MANUAL
MOTOROLA