MC68030RC33

Manufacturer Part NumberMC68030RC33
DescriptionMC68030RC33ENHANCED 32-BIT MICROPROCESSOR
ManufacturerMotorola
MC68030RC33 datasheet
 


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Page 176/602:

Synchronous Operation with STERM

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To assure proper operation in a synchronous system when BERR or BERR and HALT is
asserted after DSACKx, BERR (and HALT) must meet the appropriate setup time
(parameter #27A) prior to the falling clock edge one clock cycle after DSACKx is recognized.
This setup time is critical, and the MC68030 may exhibit erratic behavior if it is violated.
When operating synchronously, the data-in setup and hold times for synchronous cycles
may be used instead of the timing requirements for data relative to the DS signal.
The value of CIIN is latched on the rising edge of bus cycle state 4 for all cycles terminated
with DSACKx.
7.2.10 Synchronous Operation with STERM
The MC68030 supports synchronous bus cycles terminated with STERM. These cycles, for
32-bit ports only, are similar to cycles terminated with DSACKx. The main difference is that
STERM can be asserted (and data can be transferred) earlier than for a cycle terminated
with DSACKx, causing the processor to perform a minimum access time transfer in two
clock periods. However, wait cycles can be inserted by delaying the assertion of STERM
appropriately.
Using STERM instead of DSACKx in any bus cycle makes the cycle synchronous. Any bus
cycle is synchronous if:
1. Neither DSACKx nor AVEC is recognized during the cycle.
2. The port size is 32 bits.
3. Synchronous input setup and hold time requirements (specifications #60 and #61) for
STERM are met.
Burst mode operation requires the use of STERM to terminate each of its cycles. The first
cycle of any burst transfer must be a synchronous cycle as described in the preceding
paragraph. The exact timing of this cycle is controlled by the assertion of STERM, and wait
cycles can be inserted as necessary. However, the minimum cycle time is two clocks. If a
burst operation is initiated and allowed to terminate normally, the second, third, and fourth
cycles latch data on successive falling edges of the clock at a minimum. Again, the exact
timing for these subsequent cycles is controlled by the timing of STERM for each of these
cycles, and wait cycles can be inserted as necessary.
MOTOROLA
MC68030 USER’S MANUAL
Bus Operation
7-29