MC68030RC33 Motorola, MC68030RC33 Datasheet - Page 227

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MC68030RC33

Manufacturer Part Number
MC68030RC33
Description
MC68030RC33ENHANCED 32-BIT MICROPROCESSOR
Manufacturer
Motorola
Datasheet
Table 7-8. DSACK, BERR, and HALT Assertion Results
Case
Control
Asserted on Rising
No.
Signal
Edge of State
N
1
DSACKx
A
BERR
NA
HALT
NA
2
DSACKx
A
BERR
NA
HALT
A/S
3
DSACKx
NA/A
BERR
A
HALT
NA
4
DSACKx
A
BERR
NA
HALT
NA
5
DSACKx
NA/A
BERR
A
HALT
A/S
6
DSACKx
A
BERR
NA
HALT
NA
LEGEND:
N
— The number of current even bus state (e.g., S2, S4, etc.)
A
— Signal is asserted in this bus state
NA — Signal is not asserted in this state
X
— Don't care
S
— Signal was asserted in previous state and remains asserted in this state
Table 7-8 shows various combinations of control signal sequences and the resulting bus
cycle terminations. To ensure predictable operation, BERR and HALT should be negated
according to the specifications in MC68030EC/D, MC68030 Electrical Specifications .
DSACKx, BERR, and HALT may be negated after AS. If DSACKx or BERR remain asserted
into S2 of the next bus cycle, that cycle may be terminated prematurely.
The termination signal for a synchronous cycle is STERM. An analogous set of bus cycle
termination cases exists in relationship to STERM assertion. Note that STERM and
DSACKx must never both be asserted in the same cycle. STERM has setup time (#60) and
hold time (#61) requirements relative to each rising edge of the processor clock while AS is
asserted. Bus error and retry terminations during burst cycles operate as described in
6.1.3.2 Burst Mode Filling, 7.5.1 Bus Errors, and 7.5.2 Retry Operation.
MOTOROLA
N+2
S
Normal cycle terminate and continue.
NA
X
S
Normal cycle terminate and halt. Continue when HALT
NA
negated.
S
X
Terminate and take bus error exception, possibly
S
deferred.
NA
X
Terminate and take bus error exception, possibly
A
deferred.
NA
X
Terminate and retry when HALT negated.
S
S
X
Terminate and retry when HALT negated.
A
A
MC68030 USER’S MANUAL
Bus Operation
Result
7-81

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