MC68030RC33 Motorola, MC68030RC33 Datasheet - Page 233

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MC68030RC33

Manufacturer Part Number
MC68030RC33
Description
MC68030RC33ENHANCED 32-BIT MICROPROCESSOR
Manufacturer
Motorola
Datasheet
S0
S2
CLK
A31-A0
FC2-FC0
SIZ1-SIZ0
R/W
ECS
OCS
AS
DS
DSACK1
DSACK0
DBEN
D31-D0
IPL0-IPL2
BERR
HALT
WRITE WITH BUS ERROR ASSERTED
Figure 7-50. Late Bus Error with DSACKx
A bus error occurring during a burst fill operation is a special case. If a bus error occurs
during the first cycle of a burst, the data is ignored, the entire cache line is marked invalid,
and the burst operation is aborted. If the cycle is for an instruction fetch, a bus error
exception is made pending. This bus error is processed only if the execution unit attempts
to use either of the two words latched during the bus cycle. If the cycle is for a data fetch,
the bus error exception is taken immediately. Refer to Section 11 Instruction Execution
Timing for more information about pipeline operation.
MOTOROLA
Sw
Sw
S4
INTERNAL
PROCESSING
MC68030 USER’S MANUAL
Bus Operation
S0
S2
S4
STACK WRITE
7-87

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