MC68030RC33

Manufacturer Part NumberMC68030RC33
DescriptionMC68030RC33ENHANCED 32-BIT MICROPROCESSOR
ManufacturerMotorola
MC68030RC33 datasheet
 
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Page 276/602:

Breakpoint Instruction Exception

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Exception Processing
The processor copies the status register, enters the supervisor privilege level, and clears
the trace bits. The processor saves the vector offset, the scanPC value (which points to the
next instruction), and the copy of the status register on the supervisor stack. It also saves
the logical address of the PMOVE instruction on the stack. Then the processor resumes
normal instruction execution after the required prefetches from the address in the exception
vector.
8.1.11 Breakpoint Instruction Exception
To use the MC68030 in a hardware emulator, it must provide a means of inserting
breakpoints in the emulator code and of performing appropriate operations at each
breakpoint. For the MC68000 and MC68008, this can be done by inserting an illegal
instruction at the breakpoint and detecting the illegal instruction exception from its vector
location. However, since the vector base register on the MC68010, MC68020, and
MC68030 allows arbitrary relocation of exception vectors, the exception address cannot
reliably identify a breakpoint. The MC68020 and MC68030 processors provide a breakpoint
capability with a set of breakpoint instructions, $4848-$484F, for eight unique breakpoints.
The breakpoint facility also allows external hardware to monitor the execution of a program
residing in the on-chip instruction cache without severe performance degradation.
When the MC68030 executes a breakpoint instruction, it performs a breakpoint
acknowledge cycle (read cycle) from CPU space type $0 with address lines A2-A4
corresponding to the breakpoint number. Refer to Figure 7-44 for the CPU space type $0
addresses and to 7.4.2 Breakpoint Acknowledge Cycle for a description of the breakpoint
acknowledge cycle. The external hardware can return either BERR, DSACKx, or STERM
with an instruction word on the data bus. If the bus cycle terminates with BERR, the
processor performs illegal instruction exception processing. If the bus cycle terminates with
DSACKx or STERM, the processor uses the data returned to replace the breakpoint
instruction in the internal instruction pipe and begins execution of that instruction. The
remainder of the pipe remains unaltered. In addition, no stacking or vector fetching is
involved with the execution of the instruction. Figure 8-7 is a flowchart of the breakpoint
instruction execution.
8-22
MC68030 USER’S MANUAL
MOTOROLA