MC68030RC33

Manufacturer Part NumberMC68030RC33
DescriptionMC68030RC33ENHANCED 32-BIT MICROPROCESSOR
ManufacturerMotorola
MC68030RC33 datasheet
 


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Exception Processing
If an address error exception occurs, the fault bits written to the stack frame are not set (they
are only set due to a bus error, as previously described), and the rerun bits alone show the
cause of the exception. Depending on the state of the pipeline, either RB and RC are both
set, or RC alone is set. To correct the pipeline contents and continue execution of the
suspended instruction, software must place the correct instruction stream data in the stage
C and/or stage B images requested by the rerun bits and clear the rerun bits. The least
significant half of the SSW applies to data cycles only. If the DF bit of the SSW is set, a data
fault has occurred and caused the exception. If the DF bit is set when the processor reads
the stack frame, it reruns the faulted data access; otherwise, it assumes that the data input
buffer value on the stack is valid for a read or that the data has been correctly written to
memory for a write (or that no data fault occurred). The RM bit of the SSW identifies a read-
modify-write operation and the RW bit indicates whether the cycle was a read or write
operation. The SIZE field indicates the size of the operand access, and the FC field specifies
the address space for the data cycle. Data and instruction stream faults may be pending
simultaneously; the fault handler should be able to recognize any combination of the FC, FB,
RC, RB, and DF bits.
8.2.2 Using Software to Complete the Bus Cycles
One method of completing a faulted bus cycle is to use a software handler to emulate the
cycle. This is the only method for correcting address errors. The handler should emulate the
faulted bus cycle in a manner that is transparent to the instruction that caused the fault. For
instruction stream faults, the handler may need to run bus cycles for both the B and C stages
of the instruction pipe. The RB and RC bits identify the stages that may require a bus cycle;
the FB and FC bits indicate that a stage was invalid when an attempt was made to use its
contents. Those stages must be repaired. For each faulted stage, the software handler
should copy the instruction word from the proper address space as indicated by the S bit of
the copy of the status register saved on the stack to the image of the appropriate stage in
the stack frame. In addition, the handler must clear the rerun bit associated with the stage
that it has corrected. The handler should not change the fault bits FB and FC.
MOTOROLA
MC68030 USER’S MANUAL
8-29