MC68030RC33

Manufacturer Part NumberMC68030RC33
DescriptionMC68030RC33ENHANCED 32-BIT MICROPROCESSOR
ManufacturerMotorola
MC68030RC33 datasheet
 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
Page 291
292
Page 292
293
Page 293
294
Page 294
295
Page 295
296
Page 296
297
Page 297
298
Page 298
299
Page 299
300
Page 300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
Page 296/602:

Translation Control

Download datasheet (4Mb)Embed
PrevNext
Memory Management Unit
Figure 9-5. Example Translation Tree Layout in Memory
9.1.1 Translation Control
The translation control register (TC) defines the size of pages in memory, selects the root
pointer register to be used for supervisor accesses, indicates whether the top level of the
translation tree is indexed by function code, and specifies the number of logical address bits
used to index into the various levels of the translation tree. The initial shift (IS) field of the
TC register defines the size of the logical address space; it contains the number of most
significant address bits that are ignored in the translation table lookup. For example, if the
IS field is set to zero, the logical address space is 2
is set to 15, the logical address space contains only 2
The page size (PS) field of the TC register specifies the page size for the system. The
number of pages in the system is equal to the logical address space divided by the page
size. The maximum number of pages that can be defined by a translation tree is greater than
32
8
16 million (2
/2
). The minimum number is 4 (2
in the table lookup, defining as many as seven regions of the above size (FC=0-6). The
entire range of the logical address space(s) can be defined by translation tables of many
sizes. The MC68030 provides flexibility that simplifies the implementation of large
translation tables.
The use of a tree structure with as many as five levels of tables provides granularity in
translation table design. The LIMIT field of the root pointer can limit the value of the first
index and limits the actual number of descriptors required. Optionally, the top level of the
structure can be indexed by function code bits. In this case, the pointer table at this level
contains eight descriptors. The next level of the structure (or the top level when the FCL bit
of the TC register is set to zero) is indexed by the most significant bits of the logical address
(disregarding the number of bits specified by the IS field). The number of logical address bits
used for this index is specified by the TIA field of the TC register. If, for example, the TIA
field contains the value 5, the index for this level contains five bits, and the pointer table at
this level contains at most 32 descriptors.
Similarly, the TIB, TIC, and TID fields of the TC register define the indexes for lower levels
of the translation table tree. When one of these fields contains zero, the remaining TIx fields
are ignored; the last nonzero TIx field defines the index into the lowest level of the tree
structure. The tables selected by the index at this level are page tables; every descriptor in
these tables is (or represents) a page descriptor. Figure 9-6 shows how the TIx fields of the
TC register apply to a function code and logical address.
Figure 9-6. Derivation of Table Index Fields
9-8
(UNABLE TO LOCATE ART)
32
bytes. On the other hand, if the IS field
32
—2
17
15
/2
). The function code can also be used
(UNABLE TO LOCATE ART)
MC68030 USER’S MANUAL
1
bytes.
MOTOROLA