MC68030RC33 Motorola, MC68030RC33 Datasheet - Page 347

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MC68030RC33

Manufacturer Part Number
MC68030RC33
Description
MC68030RC33ENHANCED 32-BIT MICROPROCESSOR
Manufacturer
Motorola
Datasheet
Memory Management Unit
Three-level translation tables are useful when the operating system makes heavy use of
shared memory spaces and/or shared page tables. Sophisticated systems often share
translation tables or program and data areas defined at the page table level. When a table
entry can point to a translation table also used by a different task, sharing memory areas
becomes efficient. The direct access to user address space by the supervisor is an example
of sharing memory.
Some artificial intelligence systems require very large virtual address spaces with only small
fragments of memory allocated among these widely differing addresses. This fragmentation
is due to the complex and recursive actions the system performs on lists of data. These
actions require the system to constantly allocate and free sophisticated pointers and linked
lists in the memory map. The fragmentation suggests a small page size to utilize memory
most efficiently. However, small pages in a large virtual memory map require relatively large
translation tables. For example, to map 4 Gbytes of virtual address space with 256-byte
pages, the page tables alone require 64 Mbytes. With a three- or four-level table structure,
the number of actual translation table entries can be drastically reduced. The designer can
use invalid descriptors to represent blocks of unused addresses and the limit fields in valid
descriptors to minimize the sizes of pointer and page tables. In addition, paging of the
address tables themselves reduces memory requirements.
9.9.3.2 INITIAL SHIFT COUNT. The initial shift field (IS) of the translation control register
(TC) can decrease the size of translation tables. When the required virtual address space
can be addressed with fewer than 32 bits, the IS field reduces the size of the virtual address
space by discarding the appropriate number of the most significant logical address bits. This
technique inhibits the system's ability to detect very large illegal (i.e., out-of-bounds)
addresses. Using the full 32-bit address and reducing the table size with invalid descriptors
and limited pointer and page table sizes prevents this problem.
MOTOROLA
MC68030 USER’S MANUAL
9-59

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