MC68030RC33

Manufacturer Part NumberMC68030RC33
DescriptionMC68030RC33ENHANCED 32-BIT MICROPROCESSOR
ManufacturerMotorola
MC68030RC33 datasheet
 
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Coprocessor Interface Description
To improve the efficiency of operand transfers between memory and the coprocessor, a
coprocessor that requires a relatively high amount of bus bandwidth or has special bus
requirements can be implemented as a DMA coprocessor. DMA coprocessors can operate
as bus masters. The coprocessor provides all control, address, and data signals necessary
to request and obtain the bus and then performs DMA transfers using the bus. DMA
coprocessors, however, must still act as bus slaves when they require information or
services of the main processor using the M68000 coprocessor interface protocol.
10.1.4.2 PROCESSOR-COPROCESSOR INTERFACE. Figure 10-2 is a block diagram of
the signals involved in an asynchronous non-DMA M68000 coprocessor interface. The
synchronous interface is similar. Since the CpID on signals A13-A15 of the address bus is
used with other address signals to select the coprocessor, the system designer can use
several coprocessors of the same type and assign a unique CpID to each one.
MAIN CONTROLLER
MC68EC030
FC2-FC0 = 111
CPU SPACE CYCLE
A19-A16 = 0010 COPROCESSOR ACCESS IN CPU SPACE
A15-A13 = xxx
COPROCESSOR IDENTIFICATION
A4-A1 = rrrr
COPROCESSOR INTERFACE REGISTER SELECTOR
Chip select logic may be integrated into the coprocessor.
*
Address lines not specified above are "0" during coprocessor access.
Figure 10-2. Asynchronous Non-DMA M68000 Coprocessor
The MC68030 accesses the registers in the CIR set using standard asynchronous or
synchronous bus cycles. Thus, the bus interface implemented by a coprocessor for its
interface register set must satisfy the MC68030 address, data, and control signal timing. The
MC68030 timing information for read and write cycles is illustrated in Figures 13-5-13-8 on
foldout pages in the back of this manual. The MC68030 never requests a burst operation
10-6
FC2-FC0
COPROCESSOR
DECODE
*
LOGIC
A19-A13
AS
DS
R/W
DSACK1/DSACK0
A4-A1
D31-D0
Interface Signal Usage
MC68030 USER’S MANUAL
CS
COPROCESSOR
ASYNCHRONOUS
BUS
INTERFACE
LOGIC
MOTOROLA