MC68030RC33 Motorola, MC68030RC33 Datasheet - Page 377
Manufacturer Part Number
MC68030RC33ENHANCED 32-BIT MICROPROCESSOR
10.2.2.3 TEST COPROCESSOR CONDITION, DECREMENT AND BRANCH
INSTRUCTION. The operation of the test coprocessor condition, decrement and branch
instruction is similar to that of the DBcc instruction provided in the M68000 Family instruction
set. This operation uses a coprocessor evaluated condition and a loop counter in the main
processor. It is useful for implementing DO-UNTIL constructs used in many high-level
10.2.2.3.1 Format. Figure 10-12 shows the format of the test coprocessor condition,
decrement and branch instruction, denoted by the cpDBcc mnemonic.
OPTIONAL COPRCESSOR-DEFINED EXTENSION WORDS
Figure 10-12. Test Coprocessor Condition, Decrement and Branch
The first word of the cpDBcc instruction is the F-line operation word. This word contains the
CpID field in bits [9-11] and 001001 in bits [8:3] to identify the cpDBcc instruction. Bits [0:2]
of this operation word specify the main processor data register used as the loop counter
during the execution of the instruction.
The second word of the cpDBcc instruction format contains the coprocessor condition
selector in bits [0-5] and should contain zeros in bits [6-15] to maintain compatibility with
future M68000 products. This word is written to the condition CIR to initiate execution of the
cpDBcc instruction by the coprocessor.
If the coprocessor requires additional information to evaluate the condition, the cpDBcc
instruction can include this information in extension words. These extension words follow
the word containing the coprocessor condition selector field in the cpDBcc instruction
The last word of the instruction contains the displacement for the cpDBcc instruction. This
displacement is a twos-complement 16-bit value that is sign-extended to long-word size
when it is used in a destination address calculation.
Instruction Format (cpDBcc)
MC68030 USER’S MANUAL
Coprocessor Interface Description