MC68030RC33

Manufacturer Part NumberMC68030RC33
DescriptionMC68030RC33ENHANCED 32-BIT MICROPROCESSOR
ManufacturerMotorola
MC68030RC33 datasheet
 


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Coprocessor Interface Description
Bit [1], the PF bit, shows the “processing finished”status of the coprocessor. That is, PF=1
indicates that the coprocessor has completed all processing associated with an instruction.
Bit [0], the TF bit, indicates the true/false condition during the execution of a conditional
category instruction. TF=1 is the true condition specifier, and TF=0 is the false condition
specifier. The TF bit is only relevant for null primitives with CA=0 that are used by the
coprocessor during the execution of a conditional instruction.
The MC68030 processes a null primitive with CA=1 in the same manner whether executing
a general or conditional category coprocessor instruction. If the coprocessor sets CA and IA
to one in the null primitive, the main processor services pending interrupts (using a mid-
instruction stack frame, refer to Figure 10-43) and reads the response CIR again. If the
coprocessor sets CA to one and IA to zero in the null primitive, the main processor reads
the response CIR again without servicing any pending interrupts.
A null, CA=0 primitive provides a condition evaluation indicator to the main processor during
the execution of a conditional instruction and ends the dialogue between the main processor
and coprocessor for that instruction. The main processor completes the execution of a
conditional category coprocessor instruction when it receives the primitive. The PF bit is not
relevant during conditional instruction execution since the primitive itself implies completion
of processing.
Usually, when the main processor reads any primitive that does not have CA=1 while
executing a general category instruction, it terminates the dialogue between the main
processor and coprocessor. If a trace exception is pending, however, the main processor
does not terminate the instruction dialogue until it reads a null, CA=0, PF=1 primitive from
the response CIR (refer to 10.5.2.5 Trace Exceptions). Thus, the main processor continues
to read the response CIR until it receives a null, CA=0, PF=1 primitive, and then performs
trace exception processing. When IA=1, the main processor services pending interrupts
before reading the response CIR again.
10-38
MC68030 USER’S MANUAL
MOTOROLA