PSB2134H Infineon Technologies AG, PSB2134H Datasheet
PSB2134H
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PSB2134H Summary of contents
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ICs for Communications Two Channel Codec Filter for Terminal Applications ® SICOFI 2-TE PSB 2132 Version 1.2 Four Channel Codec Filter for Terminal Applications ® SICOFI 4-TE PSB 2134 Version 1.2 Data Sheet 09. ...
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PSB 2132 Revision History: Previous Version: Page Page Subjects (major changes since last revision) (in previous (in current Version) Version) Feature list updated IOM ® , IOM ® -1, IOM ® -2, SICOFI ® , SICOFI ARCOFI ® -SP, EPIC ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 4.3 Out-of-Band Signals at Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 ...
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Overview The Signal Processing Codec Filter for terminal applications PSB 2132/4 SICOFI2/4- special derivative of the SIEMENS programmable codec-filter-IC family designed for terminal applications featuring two or four POTS interfaces. It can be directly connected to the ...
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Two Channel Codec Filter for Terminal Applications ® SICOFI 2-TE Four Channel Codec Filter for Terminal Applications ® SICOFI 4-TE Preliminary Data 1.1 Features • Single chip programmable CODEC and FILTER to handle two or four POTS interfaces • IOM-2 ...
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Pin Configuration (top view IN1 GNDA1 OUT1 V 52 DDA12 V 53 OUT2 GNDA2 IN2 V 56 REF V 57 DDREF N.U. 58 GNDA 59 N. DDA N.U. ...
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Pin Definition and Functions Pin No. Symbol Input (I) Output (O) Common Pins for all Channels DDD 21 GNDD DDA12 V 56 I/O REF DDREF 31 FSC I 32 ...
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Pin No. Symbol Input (I) Output (O) 19 DIN I 20 DOUT O 33 RGEN O 16 CHCLK2 O 34 INT12 O Dedicated pins for PSB 2132 DDA 59,63 GNDA I 1,2,13, N.U 3,4,5, N.U.I.O ...
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Pin No. Symbol Input (I) Output (O) Specific Pins for Channel 1 50 GNDA1 IN1 OUT1 36 SI1_0 I 35 SI1_1 I 41 SO1_0 O 40 SO1_1 O 39 SB1_0 I/O 38 SB1_1 ...
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Pin No. Symbol Input (I) Output (O) Specific Pins for Channel 3 (PSB 2134 only) 59 GNDA3 IN3 OUT3 2 SI3_0 I 1 SI3_1 I 7 SO3_0 O 6 SO3_1 O 5 SB3_0 ...
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Pin No. Symbol Input (I) Output (O) Specific Pins for Channel 4 (PSB 2134 only) 63 GNDA4 IN4 OUT4 13 SI4_0 I 14 SI4_1 I 8 SO4_0 O 9 SO4_1 O 10 SB4_0 ...
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Functional Description 2.1 System Integration The SICOFI2/4-TE is connected to an IOM-2 compatible transceiver such as the PEB 8191 INTC-Q for U-interface or NT-applications or the PSB 2186 ISAC PSB 2115 IPAC for S/T-interface applications. The FSC ...
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The microcontroller interface is connected to a microcontroller. Since the data transfer does not require duplex operation it can be connected both to SPI compatible microcontrollers (Siemens C5xx series, C161 series) as well as to Intel C51 based ones. The ...
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Figure 3 ® SICOFI 2/4-TE Signal Flow Graph (for any channel) Transmit Path The analog input signal has to be DC-free connected by an external capacitor because there is an internal virtual reference ground potential. After passing a simple antialiasing ...
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POST-Filter (POFI). As the signal virtual ground potential, an external capacitor is required for DC-decoupling. Loops There are two loops implemented. The first is ...
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The IOM-2 PCM-interface One serial PCM-interface is used for transfer -law compressed voice data. The PCM-interface consists of 4 pins: BCL: IOM-2 bit clock, 768 kHz FSC: Frame Synchronization Clock, 8 kHz DU: Data transmit or ...
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FSC B1 B2 MON0 DCL BCL DU/ Figure 5 Example for IOM-2 Terminal Mode Semiconductor Group 125 s D CI0 IC1 IC2 MON1 PSB 2132 PSB 2134 Functional ...
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The -Controller Interface The internal configuration registers, the signaling interface, and the Coefficient-RAM (CRAM) of the SICOFI-2/4-TE are programmable via a serial -Controller interface. The -Controller interface consists of four lines: CS, DCLK, DIN and DOUT used ...
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CS DCLK DIN Control High ’Z’ DOUT Figure 7 Example for a Read Access, with One Data Byte Transferred via DOUT The data transfer is synchronized by the DCLK input. The contents ...
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The Signaling Interface The SICOFI-2/4 TE signaling interface is made input pins (SIx_0, SIx_1), two output pins (SOx_0, SOx_1) and three bi-directional programmable pins (SBx_0, SBx_1, SBx_2) per channel. Tip SLIC 2 Ring Tip SLIC 1 ...
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SI4_1 SI4_0 CH4 SI3_1 SI3_0 CH3 SI2_1 SI2_0 CH2 SI1_1 SI1_0 CH1 Figure 10 The status bits of all SIx_0 and SIx_1 inputs are stored in the XR0 register (RD). Similar the control bits of SOx_0 and SOx_1 are stored ...
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SB4_2 SB4_1 CH4 SB4_0 SB3_2 CH3 SB3_1 SB3_0 SB2_2 SB2_1 CH2 SB2_0 SB1_2 SB1_1 CH1 SB1_0 Figure 11 Depending on the application, the lines can be group individually to support the best software interface. E. DTMF receiver is ...
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Tip SLIC 2 Ring Tip SLIC Ring MUX Figure 12 Additional two interrupt pins (INT12, INT34) are provided. If one of the input pins for channel one of the bi-directional pins for channel 1 and 2 ...
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Programming the SICOFI With the appropriate commands, the SICOFI2/4-TE can be programmed and verified very flexibly via the -Controller interface. With the first byte received via DIN, one of 3 different types of commands (SOP, XOP and COP) is ...
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Storage of Programming Information 6 configuration registers per channel: 8 common configuration registers: 1 Coefficient-RAM per channel: 3.2 Examples for SICOFI SOP - Write Commands DIN SOP-Write 1 Byte CR0 DIN 7 ...
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XOP - Write Commands DIN XOP-Write 2 Bytes XR1 XR0 DIN XOP-Write 3 Bytes XR2 XR1 XR0 COP - Write Commands DIN 7 6 ...
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SOP - Read Commands DIN Bit SOP-Read 1 Byte DIN Bit ...
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XOP-Read Commands DIN Bit XOP-Read 1 Byte DIN Bit ...
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COP-Read Commands DIN Bit COP-Read 4 Bytes DIN Bit ...
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Example of a Mixed Command DIN Bit SOP-Write 4 Bytes CR3 CR2 CR1 CR0 XOP-Write 2 Bytes XR1 XR0 COP-Write 4 Bytes Coeff. 3 ...
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SOP Command To modify or evaluate the SICOFI2/4-TE status, the contents configuration registers CR0 .. CR5 may be transferred to or from the SICOFI2/4-TE. This is started by a SOP-Command (status operation command). Bit 7 ...
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CR0 Configuration Register 0 Configuration register CR0 defines the basic SICOFI2/4-TE settings, which are: enabling/disabling the programmable digital filters. Bit 7 TH IM/R1 TH Enable TH- (Trans Hybrid Balancing) Filter IM/R1 Enable IM-(Impedance ...
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CR1 Configuration Register 1 Configuration register CR1 selects tone generator modes and other operation modes. Bit 7 ETG2 ETG1 ETG2 Enable programmable tone generator 2 ETG2 = 0: ETG2 = 1: ETG1 Enable programmable tone generator 1 ETG1 = ...
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CR2 Configuration Register 2 Bit 7 COT/R COT/R Selection of Cut off Transmit/Receive Paths Normal Operation COT16 COT8 COR4M COR64 IDR Initialize Data RAM ...
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Figure 13 ‘CUT OFF’s’ and Loops Semiconductor Group Programming the SICOFI 36 PSB 2132 PSB 2134 ® -2/4-TE 09.97 ...
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CR3 Configuration Register 3 Bit 7 Test-Loops Test-Loops 4 bit field for selection of Analog and Digital Loop Backs ...
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CR4 Configuration Register 4 Configuration register CR4, sets the receiving time slot and the receiving PCM-highway. Bit 7 RLINE 0 RLINE Selects the data line for the receiving of PCM-data RLINE = 0: RLINE = 1: RS[3:0] Selects the ...
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COP Command With a COP command coefficients for the programmable filters can be written to the SICOFI-2/4-TE coefficient-RAM or read from the Coefficient-RAM via the -Controller interface for verification Bit 7 AD2 AD1 AD2-1 Address AD2 ...
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How to Program the Filter Coefficients TH-Filter: Two (Four) sets of TH-filter coefficients can be loaded to the SICOFI2 (/4)-TE. Each sets can be selected for any of the two / four SICOFI2/4-TE channels, by setting the value of TH-Sel ...
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XOP Command With the XOP command the SICOFI2/4-TE digital command/indication interface to a SLIC is configured and evaluated. Also other common functions are assigned with this command. Bit 7 RST 0 RST Software Reset (same as RESET-pin, valid for ...
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XR0 Extended Register 0 The signaling connection between SICOFI2/4-TE and a SLIC is performed by master device the SICOFI2/4-TE signaling input and output pins and Configuration Register XR0... XR4. Data received from the upstream master device are transferred to ...
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Common SO2_1 Pin SO2_1 is set to the assigned value SO2_0 Pin SO2_0 is set to the assigned value SO1_1 Pin SO1_1 is set to the assigned value SO1_0 Pin SO1_0 is set to the assigned value Semiconductor Group Programming ...
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XR1 Extended Register 1 This register transfers information to or from the programmable signaling pins. Bit SB4_1 SB4_0 In Connection with a XOP-Read Command PSB 2134 only SB4_1 If input: status of pin SB4_1 is transferred ...
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XR2 Extended Register 2 This register controls the direction of the programmable signaling pins. Bit PSB4_1 PSB4_0 PSB3_1 PSB3_0 PSB2_1 PSB2_0 PSB1_1 PSB1_0 PSB 2134 only PSB4_1 Programmable bi-directional signaling pin SB4_1 is programmed PSB4_1 = ...
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PSB1_0 = 0: Pin SB1_0 is indication input PSB1_0 = 1: Pin SB1_0 is command output Note: After a ‘Reset’ of the device, all programmable pins are input pins! 3.5.4 XR3 Extended Register 3 This register transfers information to or ...
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PSB3_2 = 0: Pin SB3_2 is indication input PSB3_2 = 1: Pin SB3_2 is command output Common PSB2_2 Programmable bi-directional signaling pin SB2_2 is programmed PSB2_2 = 0: Pin SB2_2 is indication input PSB2_2 = 1: Pin SB2_2 is command ...
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Configuration of RGEN Field T Frequency applied to Pin RGEN RGEN is set to 1 permanently 2ms 4ms . . . . . . ...
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XR5 Extended Register 5 This register contains additional configuration items valid for all 2/4 channels Bit CR_DU Crash 0: 1: CR_DD Crash on DD (read only CHCLK Enables Chopper Clock Output to pin CHCLK ...
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X X R-S Receive Slope R-S= 0: R-S= 1: DRV_0 Driving Mode for Bit 0 DRV_0 = 0: DRV_0 = 1: PCM-OFFSET Offset in number of data-clock periods added to Time slot ...
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Setting of Slopes in Register XR6 FSC BCL Bit Time-Slot 0 Figure 15 Semiconductor Group 7 51 PSB 2132 PSB 2134 Programming the SICOFI Transmit Slope Receive Slope Single Clock Mode ...
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Operating Modes Power-ON, HW-Reset Standby Ch. 1 Operating Ch PSB 2134 only Figure 16 3.6.1 RESET (Basic Setting Mode) Upon initial application of software-reset (see XOP command), the SICOFI2/4-TE enters a basic setting mode. Basic setting means, ...
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Command Stack DIN-input DOUT-output VOUT1,2 or 1,2,3,4 SBx_y SOx_y If any voltage is applied to any input-pin before initial application of TE may not enter the basic setting mode. In this case it is necessary to reset the SICOFI2/4-TE or ...
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Impedance Matching Filter • Realization by 3 different loops – 4 MHz: Multiplication by a constant – 128 kHz: Wave Digital Filter (IIR) Improves low frequency response – 64 kHz: FIR-Filter For fine-tuning • Improved stability behavior of feedback loops ...
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Filters for Frequency Response Correction • For line equalization and compensation of attenuation distortion • Improvement of Group-Delay-Distortion by using minimum phase filters (instead of linear phase filters) • FRR filter for correction of receive path distortion – 5 TAP ...
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Simulation (PSPICE) Automatic K-Param Extraction Line Line Interface Interface Line Line Interface Interface ...
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SICOFI-2/4 TE and SLIC combination is calculated. If the real part of the system input impedance is positive, the total system stability can be guaranteed. In addition to the individual calculation of coefficient sets Siemens will provide ready to use ...
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Transmission Characteristics The figures in this specification are based on the subscriber-line board requirements. The proper adjustment of the programmable filters (transhybrid balancing, impedance matching, frequency-response correction) requires a complete knowledge of the SICOFI-2/4 TE’s analog environment. Unless otherwise ...
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Transmission Characteristics Parameter Gain absolute (AGX = AGR = – 70 ° Gain absolute (AGX = 6.02 dB, AGR ...
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Frequency Response Figure 18 Receive: Reference Frequency 1014 Hz, Input Signal Level 0 dBm0 Figure 19 Transmit: Reference Frequency 1014 Hz, Input Signal Level 0 dBm0 Semiconductor Group Transmission Characteristics 60 PSB 2132 PSB 2134 09.97 ...
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Group Delay Maximum delays when the SICOFI2/4-TE is operating with H(TH) = H(IM and H(FRR) = H(FRX including delay through A/D- and D/A converters. Specific filter programming may cause additional group delays. Group delay deviations ...
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Figure 21 Group Delay Distortion Receive: Input Signal Level 0 dBm0 1) HPR is switched on: reference point is at HPR is switched off: reference is at 1.5 kHz Semiconductor Group Transmission Characteristics t Gmin 62 PSB 2132 PSB 2134 ...
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Out-of-Band Signals at Analog Input With an 0 dBm0 out-of-band sine wave signal with frequency 100 kHz) applied to the analog input, the level of any resulting frequency component at the digital output will stay at least X dB ...
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Out-of-Band Signals at Analog Output With a 0 dBm0 sine wave with frequency input, the level of any resulting out-of-band signal at the analog output will stay at least X dB below a 0 dBm0, 1 kHz sine wave ...
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Out of Band Idle Channel Noise at Analog Output With an idle code applied to the digital input, the level of any resulting out-of-band power spectral density (measured with 3 kHz bandwidth) at the analog output, will be not ...
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Overload Compression Figure 25 -Law, Transmit: measured with sine wave Semiconductor Group Transmission Characteristics f = 1014 Hz. 66 PSB 2132 PSB 2134 09.97 ...
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Gain Tracking (receive or transmit) The gain deviations stay within the limits in the figures below. Figure 26 Gain Tracking: (measured with sine wave Semiconductor Group Transmission Characteristics f = 1014 Hz, reference level is 0 dBm0) 67 PSB ...
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Total Distortion The signal to distortion ratio exceeds the limits in the following figure (measured with sine wave 34 28 -60 Figure 27 Receive or Transmit: measured with ...
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Loop Back via Analog Port”. The programmable filters FRR, AR, FRX, AX and IM are disabled, the balancing filter TH is enabled with coefficients optimized for V this configuration ( = OUT The resulting echo measured at the ...
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Proposed Test Circuit IN4 OUT4 63 GNDA4 * IN4 OUT4 DDA34 DDA34 OUT3 OUT3 * 59 GNDA3 ...
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Guidelines for Board-Design 6.1 Board Layout Recommendation Keep in mind that inside the SICOFI-2/4 TE all the different via the substrate of the chip, and the areas connected to different grounds are separated on chip. a) Separate all digital ...
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Example of a SICOFI-2/4-TE-board SICOFI 2/4- ...
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Hz. The QSICOS-program contains a program for generating coefficients for variable frequencies. The following table shows sequences for programming both the tone generators and the bandpass-filters to select common used frequencies: Table 1 Frequency Tone Freq. 350 ...
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Application Note: Level Metering 8.1 Introduction The purpose of this application note is to describe the handling of the Level Metering Function and the facts that should be taken into account when using it. The Level Metering Function is ...
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There is a single 8-bit offset register available for all 4 channels. This offset register can be accessed as XR7 with a XOP command. With the QSICOS utility program ’Calculate Level Metering Function’ the programming byte for the register XR7 ...
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The procedure to find an unknown level is predesigned to be carried out by software. The first valid LMR-bit is available 4 ms after enabling the level metering via setting bit LM. Then the LMR-bit is updated every 4 ms ...
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The attenuation and amplification filters of the SICOFI2/4-TE can be used to amplify or attenuate the level of the tone generator 1. With disabled filters the tone generator 1 sends a level of -4.5 dBm0. In order to avoid test ...
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To calculate the applied analog level, the gain settings of the SICOFI2/4-TE filters together with the 0 dBm0 reference voltage have to be taken into consideration. Analog Test Signal Figure 34 Measurement of an unknown level 8.9 Loops If the ...
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The TAS 2100 emulates subscriber line lengths from kft in 1 kft increments. 1 kft is equivalent to 0.3 km. The SICOFI2/4-TE is programmed with the file TEST.SUC for operation with the Harris-SLIC HC 5502 and the ...
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Figure 39 shows a simplified model of a subscriber line with an analog telephone set tip C L ring subscriber line C SPEC-File of QSICOS software (circuit ...
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Appendix Appendix A: Assignment of measured level and byte for offset register XR7 Level / dBm0 Hex-Code 3.11 3.00 2.89 2.78 2.67 2.56 2.44 2.33 2.21 2.09 1.97 1.84 1.72 1.59 1.46 1.33 1.20 1.07 0.93 0.79 0.65 0.50 ...
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Level / dBm0 Hex-Code -2.80 Appendix B: File LMch1a.SUC ;SICOFI2/4-TE LEVEL METERING in channel 1, Version 1.0 by R.Kitze, January 1997 ;Configuration: SICOFI4-µC Board V1.1 STUT 2466, EVC50X Board, Harris SLIC-Board STUS ;5502 V2.0. ;Please run the file TEST.SUC (QSICOS ...
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The measured level is between the levels -9.95 dBm0 (byte 12) and -10.45 dBm0 (byte 11). Appendix C: File LMch1b.SUC ;Supervision the state of a subscriber line via LEVEL METERING in channel 1 ;Version 1.0 by R.Kitze, January ...
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offset byte = (5) ; Read CR2, CR1, CR0 ;CR2=04 indicates that the measured level is lower than the reference ...
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Appendix D: Measured levels for different line lengths Subscriber Line: Cable configuration 0 AWG Subscriber Line in kft The measured level is between the lower/higher level. Semiconductor Group ...
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Appendix E: Tone generator coefficients (bandpass Q-factor = 2) Frequency / Hz 300 600 900 1200 1500 1900 8A AC ...
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Appendix F: Cable parameters at 1 kHz Cable type Distributed capacitance C’ 0.32 mm PVC 120 nF/km 0.40 mm PVC 120 nF/km 0. nF/km 0. nF/km 0. nF/km 0.63 mm PVC ...
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Electrical Characteristics Absolute Maximum Ratings Parameter V referred to GNDD DD GNDA to GNDD Analog input and output voltage V Referred Referred to GNDA = 0 V All digital input voltages Referred to GNDD ...
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Operating Range Parameter V supply current DD standby V supply current DD Operating (1 channel) Operating (2 channels) PSB 2134 only: Operating (3 channels) Operating (4 channels) Power ...
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Analog Interface ° Parameter Analog input resistance Analog output resistance Analog output load Input leakage current Input offset voltage Output offset voltage Input voltage range (AC) Semiconductor Group 5%; ...
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Coupling Capacitors at the Analog Interface In Transmit direction capacitor has to be connected to V frequency response requirement in Receive direction, the value of the coupling capacitor (C ) needed, depends on the input resistance ...
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PCM-Interface Timing t BCL 50% BCL t t FSC_S FSC_H FSC t t DR_S DR_H DU/DD DU/DD Figure 38 Single Clocking Mode Parameter Period of BCL BCL high time Period FSC FSC setup time FSC hold time DU/DD setup ...
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Interface Timing t DCLK 50% DCLK t CS_S DIN_S DIN_H DIN DOUT Figure 39 Parameter Period of DCLK DCLK high time CS setup time CS hold time DIN setup time DIN hold time 1) DOUT ...
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Signaling Interface 9.5.1 From the C-interface to the SO/SB-pins (data downstream) Parameter 1) SO/SB delay time SB to ‘Z’ - time SB to ‘drive’-time 1) All delay times are made up by two components: an intrinsic time (min-time), caused ...
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Package Outlines P-MQFP-64 (Plastic Metric Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 95 PSB 2132 PSB 2134 Package Outlines ...