HYB39S16160AT-8 Infineon Technologies AG, HYB39S16160AT-8 Datasheet
HYB39S16160AT-8
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HYB39S16160AT-8 Summary of contents
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MBit Synchronous DRAM (second generation) Advanced Information • High Performance: CAS latency = 125 CK3 t 7 AC3 • Single Pulsed RAS Interface • Fully Synchronous to Positive Clock Edge • ...
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Ordering Information Type Ordering Code Package LVTTL-Version HYB 39S16400AT-8 Q67100-Q1333 P-TSOPII-44-1 (400 mil) 125 MHz 2B HYB 39S16400AT-10 Q67100-Q1323 P-TSOPII-44-1 (400 mil) 100 MHz 2B HYB 39S16800AT-8 Q67100-Q1335 P-TSOPII-44-1 (400 mil) 125 MHz 2B HYB 39S16800AT-10 Q67100-Q1327 P-TSOPII-44-1 (400 mil) ...
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Pin Configuration Semiconductor Group HYB 39S16400/800/160AT-8/-10 16 MBit Synchronous DRAM DQ0 SSQ DQ1 DDQ DQ2 SSQ DQ3 DDQ N. CAS ...
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Signal Pin Description Pin Type Signal Polarity Function CLK Input Pulse CKE Input Level CS Input Pulse RAS Input Pulse CAS A10 Input Level A11 (BS) Input Level DQx Input Level Output Semiconductor Group HYB 39S16400/800/160AT-8/-10 Positive ...
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Signal Pin Description (cont’d) Pin Type Signal Polarity Function DQM Input Pulse LDQM UDQM V Supply – Supply – DDQ V SSQ Semiconductor Group HYB 39S16400/800/160AT-8/-10 Active The Data Input/Output mask places the DQ buffers in ...
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CKE CKE Buffer Refresh Clock Row Address Counter CLK CLK Buffer A10 A11 (BS Buffer RAS RAS Buffer CAS CAS Buffer WE WE Buffer DQM DQM ...
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CKE CKE Buffer Self Refresh Clock Row Address Counter CLK CLK Buffer A10 A11 (BS Buffer RAS RAS Buffer CAS CAS Buffer WE WE Buffer DQM ...
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CKE CKE Buffer Self Refresh Clock Row Address Counter CLK CLK Buffer A10 A11 (BS Buffer RAS RAS Buffer CAS CAS Buffer WE WE Buffer UDQM ...
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Operation Definition All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the positive edge of the clock. The following list shows the most important operation commands. Operation Standby, Ignore RAS, CAS, ...
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BS A10 A9 A8 Operation Mode Operation Mode M11 M10 Multiple Burst with Single CAS Latency ...
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Read and Write Access Mode When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle starts. According to address data, a word line of the selected bank is activated ...
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DQM Function DQM has two functions for data I/O read write operations. During reads, when it turns to high at a clock timing, data outputs are disabled and become high impedance after two clock delay (DQM t Data Disable Latency ...
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Bank Selection by Address Bits A10 Bank A only Low Bank B only Low Both A and B High Burst Termination Once a burst read or write operation has been initiated, there are several methods in which to terminate the ...
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Absolute Maximum Ratings Operating temperature range ........................................................................................ Storage temperature range..................................................................................... – 150 C Input/output voltage .......................................................................... – 0.5 to min ( V V Power supply voltage / DD Power Dissipation ....................................................................................................................... 1 ...
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Operating Currents 3 (Recommended Operating Conditions unless otherwise noted) Parameter Symbol Test Condition I Operating current CC1 I Precharge CC2P Standby current in Power Down I CC2PS Mode ...
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AC Characteristics Parameter Clock and Clock Enable Clock Cycle time CAS Latency = 3 CAS Latency = 2 CAS Latency = 1 System frequency CAS ...
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AC Characteristics (cont’ Parameter Common Parameters Row to Column Delay time Row Active time Precharge time Row Cycle time Bank to Bank delay time CAS to CAS ...
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Notes 1. All voltages are referenced may overshoot – 2.0 V for pulse width < 4.0 ns with 3.3 V. Pulse width measured points with amplitude measured peak to DC ...
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CLOCK t HOLD t SETUP INPUT OUTPUT Semiconductor Group HYB 39S16400/800/160AT-8/- 2 SPT03404 19 16 MBit Synchronous ...
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Clock Frequency and Latency Parameter Clock frequency Clock Cycle time CAS latency Row to Column delay RAS latency Row Active time Row Precharge time Row Cycle time Last Data-In to Precharge (Write Recovery) Last Data-In to Active/Refresh Bank to Bank ...
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Package Outlines Plastic Package P-TSOPII-44 (400 mil, 0.8 mm lead pitch) Thin Small Outline Package, SMD 0.8 21x 3) +0.1 0.35 -0. 2.5 max 18.41 Index Marking 1) Does not include plastic or metal protrusion of 0.15 max ...
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Plastic Package P-TSOPII-50 (400 mil, 0.8 mm lead pitch) Thin Small Outline Package, SMD + 0.05 0 Index Marking 1) Does not include plastic or metal protrusion of 0.25 max. per side Sorts of Packing Package ...