HYB3165165ATL-50 Infineon Technologies AG, HYB3165165ATL-50 Datasheet

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HYB3165165ATL-50

Manufacturer Part Number
HYB3165165ATL-50
Description
4M x 16bit DRAM
Manufacturer
Infineon Technologies AG
Datasheet
Advanced Information
Semiconductor Group
4M x 16-Bit Dynamic RAM
(8k, 4k & 2k Refresh, EDO-Version)
4 194 304 words by 16-bit organization
0 to 70 °C operating temperature
Hyper Page Mode - EDO - operation
Performance:
Single + 3.3 V ( 0.3V) power supply
Low power dissipation:
7.2
3.24 mW standby (MOS)
720
Read, write, read-modify-write, CAS-before-RAS refresh (CBR),
RAS-only refresh, hidden refresh and Self Refresh (L-version only
2 CAS / 1 WE byte control
8192 refresh cycles/128 ms , 13 R/ 9C addresses (HYB 3164165AT)
4096 refresh cycles/ 64 ms , 12 R/ 10C addresses (HYB 3165165AT)
2048 refresh cycles/ 32 ms , 11 R/ 11C addresses
256ms refresh period for L-versions
Plastic Package:
HYB3166165AT(L)
HYB3165165AT(L)
HYB3164165AT(L)
mW standby (TTL)
t
t
t
t
t
RAC
CAC
AA
RC
HPC
A standby for L-version
RAS access time
CAS access time
Access time from address
Read/write cycle time
Hyper page mode (EDO)
cycle time
P-TSOPII-50 400 mil
1008
756
612
-40
-40
40
10
20
69
16
1
612
504
324
-50
-50
50
13
25
84
20
HYB 3165165AT(L) -40/-50/-60
HYB 3164165AT(L) -40/-50/-60
HYB 3166165AT(L) -40/-50/-60
450
360
324
-60
(HYB 3166165AT)
-60
60
15
30
104
25
mW
mW
mW
ns
ns
ns
ns
ns
6.97

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HYB3165165ATL-50 Summary of contents

Page 1

Dynamic RAM (8k, 4k & 2k Refresh, EDO-Version) Advanced Information 4 194 304 words by 16-bit organization • °C operating temperature • Hyper Page Mode - EDO - operation • Performance: • t RAS ...

Page 2

This device MBit dynamic RAM organized 4 194 304 x 16 bits. The device is fabricated on an advanced first generation 64Mbit 0,35 m CMOS silicon gate process technology. The circuit and process design allow this device ...

Page 3

Pin Configuration VCC I/O1 I/O2 I/O3 I/O4 VCC I/O5 I/O6 I/O7 I/O8 N.C. VCC WE RAS N.C. N.C. N.C. N. VCC * Pin 33 is A12 for HYB 3164165AT(L) and N.C. for HYB 3165(6)165AT(L) ...

Page 4

TRUTH TABLE FUNCTION RAS LCAS UCAS WE H Standby Read:Word L Read:Lower Byte L Read:Upper Byte L Write:Word L (Early-Write) L Write:Lower Byte (Early-Write) Write:Upper Byte L (Early Write) Read-Modify- L Write Hyper Page Mode 1st L Read (Word) Cycle ...

Page 5

WE . UCAS . LCAS No. 2 Clock Generator Column 9 Address Buffer( Refresh Controller Refresh Counter (13 A10 A11 Row A12 13 Address Buffers(13) No. 1 Clock RAS Generator ...

Page 6

WE . UCAS . LCAS No. 2 Clock Generator Column 10 Address Buffer(10 Refresh Controller Refresh Counter (12 A10 A11 Row 12 Address Buffers(12) No. 1 Clock RAS Generator Block ...

Page 7

WE . UCAS . LCAS No. 2 Clock Generator Column 11 Address Buffer(11 Refresh Controller Refresh Counter (11 A10 Row 11 Address Buffers(11) No. 1 Clock RAS Generator Block Diagram ...

Page 8

Absolute Maximum Ratings Operating temperature range.............................................................................................. °C Storage temperature range.........................................................................................– 150 °C Input/output voltage..................................................................................-0.5 to min (Vcc+0.5,4.6) V Power supply voltage....................................................................................................-0.5V to 4.6 V Power dissipation......................................................................................................................1.3 W Data out current (short circuit)..................................................................................................50 mA Note Stresses above ...

Page 9

DC-Characteristics (cont’ ° Parameter Operating Current - (RAS, CAS, address cycling: tRC = tRC min.) Standby Current ( = RAS CAS RAS Only Refresh Current: - (RAS cycling: ...

Page 10

AC Characteristics ° Parameter Common Parameters Random read or write cycle time RAS pulse width CAS pulse width RAS precharge time CAS precharge time Row address setup time ...

Page 11

AC Characteristics (cont’ ° Parameter Read command hold time referenced to RAS CAS to output in low-Z Output buffer turn-off delay Output buffer turn-off delay from OE t Data ...

Page 12

AC Characteristics (cont’ ° Parameter RAS pulse width in hyper page mode t CAS precharge to RAS Delay OE pulse width OE hold time from CAS high Output buffer ...

Page 13

Notes: 1) All voltages are referenced to VSS. Vih may overshoot to Vcc + 2.0 V for pulse widths of < 4ns with 3.3V. Vil may undershoot to -2.0V for pulse width < 4.0 ns with 3.3V. Pulse width measured ...

Page 14

V IH RAS UCAS IH LCAS ASR V AAAA AAA AAAA AAA IH AAAA AAA Row AAAA AAA Address AAAA AAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA ...

Page 15

V IH RAS V IL UCAS V IH LCAS ASR V AAAA AAA AAAA AAA IH AAAA AAA Row AAAA AAA Address AAAA AAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA ...

Page 16

V IH RAS V IL UCAS V IH LCAS ASR V AAAA AAAA A AAAA AAAA AAAA AAAA AAAA AAAA A A Row Address AAAA AAAA AAAA AAAA AAAA AAAA A ...

Page 17

V IH RAS UCAS IH LCAS ASR V AAA A IH AAA A Address AAA A A Row AAA AAA AAA V AAA AAAA AAAA AAAA AAA AAAA AAAA AAAA ...

Page 18

V IH RAS CRP V UCAS IH LCAS RAH t ASR V AAAA A IH AAAA A AAAA A A Address AAAA Row AAAA AAAA t RAD AAAA AAAA AAAA ...

Page 19

V IH RAS CRP V IH UCAS V IL LCAS t RAH t ASR V AAAA AAAA AAAA A A Address AAAA Row AAAA AAAA t RAD AAAA AAAA AAAA ...

Page 20

V IH RAS CRP V IH UCAS V IL LCAS t RAH t ASR V AAAA A AAAA A IH AAAA A Address AAAA A A Row AAAA AAAA AAAA t RAD AAAA ...

Page 21

V IH RAS CRP V IH UCAS V IL LCAS t RAH t ASR V AAAA A IH AAAA A Row Address AAAA A A AAAA AAAA A A Addr V IL AAAA t t WCS AAAA ...

Page 22

V IH RAS CRP V IH UCAS V IL LCAS t RAH t ASR V AAAA AAAA AAAA A A Address AAAA Row AAAA AAAA t RAD AAAA AAAA AAAA ...

Page 23

Hyper Page Mode (EDO) Read-Modify-Write Cycle Semiconductor Group HYB3164(5/6)165AT(L)-40/-50/-60 AAAA AA AAAA AA AAAA AA AAAA AA AA AAAA AAAA AA AAAA AA AAAA AA AA AAAA AAAA AA AAAA AA AA AAAA AAAA AA AAAA A AAAA AA AAAA ...

Page 24

V IH RAS UCAS IH LCAS ASR V AAAA AAAA AAAA IH AAAA AAAA AAAA AAAA AAAA AAAA Address AAAA AAAA AAAA AAAA AAAA AAAA V IL AAAA AAAA AAAA V OH I/O (Outputs) ...

Page 25

V IH RAS RPC UCAS V IL LCAS V AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA IH AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA WE AAAA AAAA AAAA AAAA AAAA AAAA ...

Page 26

V IH RAS UCAS LCAS RAD t RAH t ASR V AAAA AAA AAAA IH AAAA AAA AAAA AAAA AAA AAAA Address AAAA AAA AAAA Row AAAA AAA AAAA V IL AAAA AAA ...

Page 27

V IH RAS UCAS V IL LCAS t RAH t ASR V AAAA AAA IH AAAA AAA AAAA AAA Address AAAA AAA Row AAAA AAA V IL AAAA AAA V AAAA AAAA AAAA AAAA AAAA AAAA ...

Page 28

V IH RAS RPC UCAS V IL LCAS V AAAA AAAA AAAA AAAA AAAA AAAA IH AAAA AAAA AAAA WE AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA ...

Page 29

Package Outlines Plastic Package P-TSOPII-50 (400 mil) (Thin Small Outline, SMD) Semiconductor Group HYB3164(5/6)165AT(L)-40/-50/- EDO-DRAM 29 ...

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