IDT72235LB20PF Integrated Device Technology, Inc., IDT72235LB20PF Datasheet

IDT72235LB20PF

Manufacturer Part Number

IDT72235LB20PF

Description

IDT72235LB20PFCMOS SyncFIFOO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18

Manufacturer

Integrated Device Technology, Inc.

Datasheet

1.IDT72235LB20PF.pdf (16 pages)

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IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™

256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18

FEATURES:

• 256 x 18-bit organization array (IDT72205LB)

• 512 x 18-bit organization array (IDT72215LB)

• 1,024 x 18-bit organization array (IDT72225LB)

• 2,048 x 18-bit organization array (IDT72235LB)

• 4,096 x 18-bit organization array (IDT72245LB)

• 10 ns read/write cycle time

• Empty and Full flags signal FIFO status

• Easily expandable in depth and width

• Asynchronous or coincident read and write clocks

• Programmable Almost-Empty and Almost-Full flags with

• Half-Full flag capability

• Dual-Port zero fall-through time architecture

• Output enable puts output data bus in high-impedance

• High-performance submicron CMOS technology

• Available in a 64-lead thin quad flatpack (TQFP/STQFP)

• Industrial temperature range (–40 C to +85 C) is available

DESCRIPTION:

are very high-speed, low-power First-In, First-Out (FIFO)

memories with clocked read and write controls. These FIFOs

FUNCTIONAL BLOCK DIAGRAM

SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

default settings

state

and plastic leaded chip carrier (PLCC)

Integrated Device Technology, Inc.

The IDT72205LB/72215LB/72225LB/72235LB/72245LB

查询IDT72205LB供应商

(

EXPANSION LOGIC

WRITE CONTROL

WRITE POINTER

RESET LOGIC

LOGIC

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

WCLK

CMOS SyncFIFO™

256 x 18, 512 x 18, 1,024 x 18,

2,048 x 18 and 4,096 x 18

OUTPUT REGISTER

1,024 x 18, 2,048 x 18

256 x 18, 512 x 18

INPUT REGISTER

RAM ARRAY

4,096 x 18

Q0-Q17

D0-D17

are applicable for a wide variety of data buffering needs, such

as optical disk controllers, Local Area Networks (LANs), and

interprocessor communication.

port is controlled by a free-running clock (WCLK), and an input

enable pin (

every clock when

by another clock pin (RCLK) and another enable pin (

read clock can be tied to the write clock for single clock

operation or the two clocks can run asynchronous of one

another for dual-clock operation. An Output Enable pin (

provided on the read port for three-state control of the output.

Full (

and Almost-Full (

flags is controlled by a simple state machine, and is initiated by

asserting the Load pin (

when the FIFO is used in a single device configuration.

technique. The XI and

In depth expansion configuration,

device and set to HIGH for all other devices in the Daisy Chain.

fabricated using IDT’s high-speed submicron CMOS technol-

ogy.

• •

These FIFOs have 18-bit input and output ports. The input

The synchronous FIFOs have two fixed flags, Empty (

These devices are depth expandable using a Daisy-Chain

The IDT72205LB/72215LB/72225LB/72235LB/72245LB is

), and two programmable flags, Almost-Empty (

WEN

PAF

). Data is read into the synchronous FIFO on

WEN

Commercial And Industrial Temperature Ranges

). The offset loading of the programmable

OFFSET REGISTER

is asserted. The output port is controlled

READ CONTROL

READ POINTER

RCLK

pins are used to expand the FIFOs.

). A Half-Full flag (

LOGIC

FLAG

is grounded on the first

IDT72205LB

IDT72215LB

IDT72225LB

IDT72235LB

IDT72245LB

2766 drw 01

) is available

MAY 2000

REN

DSC-2766/-

). The

PAE

) and

)

) is

)

Related parts for IDT72235LB20PF

IDT72235LB20PF Summary of contents

Page 1

... RESET LOGIC SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ©2000 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391. CMOS SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, ...

Page 2

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 PIN CONFIGURATIONS V GND PIN ...

Page 3

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 PIN DESCRIPTION Symbol Name D0–D17 Data Inputs RS Reset WCLK Write Clock WEN Write Enable RCLK Read Clock REN Read Enable ...

Page 4

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 ABSOLUTE MAXIMUM RATINGS Symbol Rating V Terminal Voltage TERM with respect to GND T Storage STG Temperature I DC Output Current ...

Page 5

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 ELECTRICAL CHARACTERISTICS (Commercial 10 +70 C; Industrial Symbol Parameter ...

Page 6

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 SIGNAL DESCRIPTIONS: INPUTS: DATA Data inputs for 18-bit wide data. CONTROLS ...

Page 7

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 WEN When the pin is LOW and is disabled; then a signal at this input can neither increment the write ...

Page 8

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 After half of the memory is filled, and at the LOW-to-HIGH transition of the next write cycle, the Half-Full Flag goes ...

Page 9

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 WCLK SKEW1 RCLK NOTES the minimum time between a rising RCLK ...

Page 10

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 WCLK (first valid write ENS RCLK ...

Page 11

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 WCLK t DS DATA WRITE ENS t ENH t t SKEW2 RCLK LOW Q ...

Page 12

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 WCLK RCLK NOTE: PAE offset. Number of data words written into FIFO already = n. WCLK D – ...

Page 13

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 WCLK t ENS NOTE: 1. Write to Last Physical Location. RCLK t ENS NOTE: 1. Read from Last Physical Location. WCLK ...

Page 14

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 OPERATING CONFIGURATIONS SINGLE DEVICE CONFIGURATION A single IDT72205LB/72215LB/72225LB/72235LB/72245LB may be used when the application requirements are for 256/ WRITE CLOCK (WCLK) ...

Page 15

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 DEPTH EXPANSION CONFIGURATION (WITH PROGRAMMABLE FLAGS) These devices can easily be adapted to applications requir- ing more than 256/512/1,024/2,048/4,096 words of ...

Page 16

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 ORDERING INFORMATION IDT XXXXX X XX Device Type Power Speed NOTE: 1. Industrial temperature range is available as standard product for ...

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