SC16C2550IA44 Philips Semiconductors, SC16C2550IA44 Datasheet
SC16C2550IA44
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SC16C2550IA44 Summary of contents
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SC16C2550 Dual UART with 16 bytes of transmit and receive FIFOs and infrared (IrDA) encoder/decoder Rev. 03 — 19 June 2003 1. Description The SC16C2550 channel Universal Asynchronous Receiver and Transmitter (UART) used for serial data communications. ...
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... Ordering information Type number Package Name Description SC16C2550IN40 DIP40 plastic dual in-line package; 40 leads (600 mil) SC16C2550IA44 PLCC44 plastic leaded chip carrier; 44 leads SC16C2550IB48 LQFP48 plastic low profile quad flat package; 48 leads; body 7 9397 750 11621 Product data Dual UART with 16 bytes of transmit and receive FIFOs and IrDA ...
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... Philips Semiconductors 4. Block diagram SC16C2550 D0–D7 DATA BUS IOR AND IOW CONTROL LOGIC RESET A0–A2 REGISTER CSA SELECT CSB LOGIC INTA, INTB INTERRUPT TXRDYA, TXRDYB CONTROL RXRDYA, RXRDYB LOGIC Fig 1. SC16C2550 block diagram. 9397 750 11621 Product data Dual UART with 16 bytes of transmit and receive FIFOs and IrDA ...
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... Philips Semiconductors 5. Pinning information 5.1 Pinning Fig 2. DIP40 pin configuration. 9397 750 11621 Product data Dual UART with 16 bytes of transmit and receive FIFOs and IrDA RXB 9 32 RXA 10 31 ...
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... Philips Semiconductors Fig 3. PLCC44 pin configuration. 9397 750 11621 Product data Dual UART with 16 bytes of transmit and receive FIFOs and IrDA RXB 10 11 RXA SC16C2550IA44 TXRDYB 12 TXA 13 TXB 14 OP2B 15 CSA 16 CSB 17 Rev. 03 — 19 June 2003 SC16C2550 encoder/decoder ...
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... Philips Semiconductors Fig 4. LQFP48 pin configuration. 5.2 Pin description Table 2: Pin description Symbol Pin DIP40 PLCC44 LQFP48 CSA, CSB 14, 15 16, 17 10, 11 D0-D7 1-8 2-9 44-48, 1-3 GND 9397 750 11621 Product data Dual UART with 16 bytes of transmit and receive FIFOs and IrDA ...
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... Philips Semiconductors Table 2: Pin description …continued Symbol Pin DIP40 PLCC44 LQFP48 INTA, 30, 29 33, 32 30, 29 INTB IOR IOW OP2A, 31, 13 35, 15 32, 9 OP2B RESET RXRDYA, - 34, 23 31, 18 RXRDYB TXRDYA 43, 6 TXRDYB XTAL1 9397 750 11621 ...
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... Philips Semiconductors Table 2: Pin description …continued Symbol Pin DIP40 PLCC44 LQFP48 XTAL2 CDA, 38, 19 42, 21 40, 16 CDB CTSA, 36, 25 40, 28 38, 23 CTSB DSRA, 37, 22 41, 25 39, 20 DSRB DTRA, 33, 34 37, 38 34, 35 DTRB RIA, RIB 39, 23 43, 26 41, 21 RTSA, 32, 24 36, 27 ...
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... Philips Semiconductors 6. Functional description The SC16C2550 provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. Synchronization for the serial data stream is accomplished by adding start and stop bits to the transmit data to form a data character (character orientated protocol) ...
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... Philips Semiconductors Table 3: Chip Select CSA-CSB = 1 CSA = 0 CSB = 0 6.2 Internal registers The SC16C2550 provides two sets of internal registers (A and B) consisting of 12 registers each for monitoring and controlling the functions of each channel of the UART. These registers are shown in holding registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO ...
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... Philips Semiconductors 6.3 FIFO operation The 16 byte transmit and receive data FIFOs are enabled by the FIFO Control Register (FCR) bit 0. The user can set the receive trigger level via FCR bits 6-7, but not the transmit trigger level. The receiver FIFO section includes a time-out function to ensure data is delivered to the external CPU ...
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... Philips Semiconductors the SC16C2550 compares two consecutive receive characters with two software flow control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above described flow control mechanisms, flow control characters are not placed (stacked) in the user accessible RX data buffer or FIFO. ...
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... Philips Semiconductors receive holding register (RHR) is read. The actual time-out value is 4 character time, including data information length, start bit, parity bit, and the size of stop bit, i.e 1 bit times. 6.8 Programmable baud rate generator The SC16C2550 supports high speed modem technologies that have increased input data rates by employing data compression schemes ...
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... Philips Semiconductors Table 6: Output baud rate 50 75 110 150 300 600 1200 2400 3600 4800 7200 9600 19.2 k 38.4 k 57.6 k 115.2 k 6.9 DMA operation The SC16C2550 FIFO trigger level provides additional flexibility to the user for block mode operation. LSR[5,6] provide an indication when the transmitter is empty or has an empty location(s) ...
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... Philips Semiconductors data that is then made available at the user data interface D0-D7. The user optionally compares the received data to the initial transmitted data for verifying error-free operation of the UART TX/RX circuits. In this mode, the receiver and transmitter interrupts are fully operational. The Modem Control Interrupts are also operational ...
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... Philips Semiconductors 7. Register descriptions Table 7 assigned bit functions are more fully defined in Table 7: SC16C2550 internal registers Shaded bits are only accessible when EFR[4] is set. [ Register Default [2] General Register Set RHR THR IER FCR ...
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... Philips Semiconductors 7.1 Transmit (THR) and Receive (RHR) Holding Registers The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and Transmit Shift Register (TSR). The status of the THR is provided in the Line Status Register (LSR). Writing to the THR transfers the contents of the data bus (D7-D0) to the TSR and UART via the THR, providing that the THR is empty. The THR empty fl ...
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... Philips Semiconductors Table 8: Bit 7.2.1 IER versus Transmit/Receive FIFO interrupt mode operation When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1) are enabled, the receive interrupts and register status will reflect the following: • The receive RXRDY interrupt (Level 2 ISR interrupt) is issued to the external CPU when the receive FIFO has reached the programmed trigger level ...
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... Philips Semiconductors 7.2.2 IER versus Receive/Transmit FIFO polled mode operation When FCR[0] = logic 1, resetting IER[0-3] enables the SC16C2550 in the FIFO polled mode of operation. In this mode, interrupts are not generated and the user must poll the LSR register for TX and/or RX data status. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s) ...
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... Philips Semiconductors 7.3.2 FIFO mode Table 9: Bit 7-6 5 9397 750 11621 Product data Dual UART with 16 bytes of transmit and receive FIFOs and IrDA FIFO Control Register bits description Symbol Description FCR[7] RCVR trigger. These bits are used to set the trigger level for the (MSB), receive FIFO interrupt ...
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... Philips Semiconductors Table 9: Bit 1 0 Table 10: FCR[ 7.4 Interrupt Status Register (ISR) The SC16C2550 provides four levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with four interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced ...
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... Philips Semiconductors Table 12: Bit 7-6 5-4 3-1 0 7.5 Line Control Register (LCR) The Line Control Register is used to specify the asynchronous data communication format. The word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. Table 13: Bit 7 6 5-3 2 1-0 9397 750 11621 ...
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... Philips Semiconductors Table 14: LCR[ Table 15: LCR[ Table 16: LCR[ 9397 750 11621 Product data Dual UART with 16 bytes of transmit and receive FIFOs and IrDA LCR[5-3] parity selection LCR[4] LCR[3] Parity selection parity 0 1 ODD parity 1 1 EVEN parity ...
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... Philips Semiconductors 7.6 Modem Control Register (MCR) This register controls the interface with the modem or a peripheral device. Table 17: Bit 9397 750 11621 Product data Dual UART with 16 bytes of transmit and receive FIFOs and IrDA Modem Control Register bits description ...
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... Philips Semiconductors 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16C2550 and the CPU. Table 18: Bit 9397 750 11621 Product data Dual UART with 16 bytes of transmit and receive FIFOs and IrDA Line Status Register bits description ...
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... Philips Semiconductors Table 18: Bit 1 0 7.8 Modem Status Register (MSR) This register provides the current state of the control interface signals from the modem, or other peripheral device to which the SC16C2550 is connected. Four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a control input from the modem changes state ...
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... Philips Semiconductors Table 19: Bit 1 0 [1] Whenever any MSR bit 0-3 is set to logic 1, a Modem Status Interrupt will be generated. 7.9 Scratchpad Register (SPR) The SC16C2550 provides a temporary data register to store 8 bits of user information. 7.10 Enhanced Feature Register (EFR) Enhanced features are enabled or disabled using this register. ...
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... Philips Semiconductors Table 20: Bit 5 4 3-0 Table 21: Cont [1] When using a software flow control the Xon/Xoff characters cannot be used for data transfer. 9397 750 11621 Product data Dual UART with 16 bytes of transmit and receive FIFOs and IrDA Enhanced Feature Register bits description ...
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... Philips Semiconductors 7.11 SC16C2550 external reset condition Table 22: Register IER FCR ISR LCR MCR LSR MSR SPR DLL DLM Table 23: Output TXA, TXB OP2A, OP2B RTSA, RTSB DTRA, DTRB INTA, INTB 8. Limiting values Table 24: In accordance with the Absolute Maximum Rating System (IEC 60134). ...
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... Philips Semiconductors 9. Static characteristics Table 25: DC electrical characteristics + 2 5.0 V 10%, unless otherwise specified. amb CC Symbol Parameter V LOW-level clock input voltage IL(CK) V HIGH-level clock input voltage IH(CK) V LOW-level input voltage IL (except X1 clock) V HIGH-level input voltage IH (except X1 clock) V LOW-level output voltage ...
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... Philips Semiconductors 10. Dynamic characteristics Table 26: AC electrical characteristics + 2 5.0 V 10%, unless otherwise specified. amb CC Symbol Parameter clock pulse duration oscillator/clock frequency 3w t address set-up time 6s t address hold time 6h t IOR delay from chip select ...
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... Philips Semiconductors 10.1 Timing diagrams A0– CSx t 13d IOW D0–D7 Fig 7. General write timing. A0– CSx t 7d IOR D0–D7 Fig 8. General read timing. 9397 750 11621 Product data Dual UART with 16 bytes of transmit and receive FIFOs and IrDA t 6h VALID ...
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... Philips Semiconductors IOW ACTIVE RTS CHANGE OF STATE DTR DCD CTS DSR INT IOR RI Fig 9. Modem input/output timing EXTERNAL CLOCK Fig 10. External clock timing. 9397 750 11621 Product data Dual UART with 16 bytes of transmit and receive FIFOs and IrDA t 17d CHANGE OF STATE ...
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... Philips Semiconductors START BIT RX INT IOR Fig 11. Receive timing. 9397 750 11621 Product data Dual UART with 16 bytes of transmit and receive FIFOs and IrDA DATA BITS (5- DATA BITS 6 DATA BITS 7 DATA BITS 16 BAUD RATE CLOCK Rev. 03 — 19 June 2003 ...
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... Philips Semiconductors START BIT RX RXRDY IOR Fig 12. Receive ready timing in non-FIFO mode. START BIT RX RXRDY IOR Fig 13. Receive ready timing in FIFO mode. 9397 750 11621 Product data Dual UART with 16 bytes of transmit and receive FIFOs and IrDA DATA BITS (5– ...
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... Philips Semiconductors START BIT TX INT t 23d ACTIVE IOW Fig 14. Transmit timing. 9397 750 11621 Product data Dual UART with 16 bytes of transmit and receive FIFOs and IrDA DATA BITS (5– DATA BITS 6 DATA BITS 7 DATA BITS ACTIVE TX READY t 22d 16 BAUD RATE CLOCK Rev. 03 — ...
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... Philips Semiconductors START BIT TX ACTIVE IOW D0–D7 BYTE #1 t 27d TXRDY TRANSMITTER Fig 15. Transmit ready timing in non-FIFO mode. 9397 750 11621 Product data Dual UART with 16 bytes of transmit and receive FIFOs and IrDA DATA BITS (5- ACTIVE TRANSMITTER READY NOT READY Rev. 03 — ...
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... Philips Semiconductors START BIT TX ACTIVE IOW D0–D7 BYTE #16 t 27d TXRDY Fig 16. Transmit ready timing in FIFO mode (DMA mode ‘1’). 9397 750 11621 Product data Dual UART with 16 bytes of transmit and receive FIFOs and IrDA DATA BITS (5- ...
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... Philips Semiconductors 11. Package outline DIP40: plastic dual in-line package; 40 leads (600 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT b max. min. max. 1.70 mm 4.7 0.51 4 1.14 0.067 inches 0.19 0.02 0.16 0.045 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...
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... Philips Semiconductors PLCC44: plastic leaded chip carrier; 44 leads pin 1 index DIMENSIONS (mm dimensions are derived from the original inch dimensions UNIT max. min. 4.57 0.81 0.53 mm 0.51 0.25 3.05 4.19 0.33 0.66 0.180 0.021 0.032 inches 0.02 0.01 0.12 0.165 0.026 0.013 Note 1 ...
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... Philips Semiconductors LQFP48: plastic low profile quad flat package; 48 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 0.27 1.6 mm 0.25 0.05 1.35 0.17 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... Philips Semiconductors 12. Soldering 12.1 Introduction This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mount components are mixed on one printed-circuit board ...
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... Philips Semiconductors – for packages with a thickness – for packages with a thickness < 2.5 mm and a volume thick/large packages. • below 235 C (SnPb process) or below 260 C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm Moisture sensitivity precautions, as indicated on packing, must be respected at all times ...
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... Surface mount [1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. [2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26 ...
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... Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. ...
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... Philips Semiconductors Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 Functional description . . . . . . . . . . . . . . . . . . . 9 6.1 UART A-B functions . . . . . . . . . . . . . . . . . . . . . 9 6.2 Internal registers 6.3 FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . 11 6.4 Hardware flow control . . . . . . . . . . . . . . . . . . . 11 6.5 Software flow control . . . . . . . . . . . . . . . . . . . 11 6.6 Special feature software flow control . . . . . . . 12 6.7 Hardware/software and time-out interrupts ...