IDT79RV4640-133MU Integrated Device Technology, Inc., IDT79RV4640-133MU Datasheet

no-image

IDT79RV4640-133MU

Manufacturer Part Number
IDT79RV4640-133MU
Description
IDT79RV4640-133MULow-Cost Embedded 64-bit RISController w/ DSP Capability
Manufacturer
Integrated Device Technology, Inc.
Datasheet

Specifications of IDT79RV4640-133MU

Case
QFP
Dc
97+
Features
Features
Features
Features
Block Diagram
Block Diagram
Block Diagram
Block Diagram
The IDT logo is a registered trademark and RC4600, RC4650, RC3081,RC3052,RC3051,RC3041 RISController, and RISCore are trademarks of Integrated Device Technology, Inc.
2001 Integrated Device Technology, Inc.
查询IDT79R4640供应商
– 64-bit integer operations
– 64-bit registers
– Based on the MIPS RISC Architecture
– 100MHz, 133MHz, 150MHz, 180MHz, 200MHz and 267MHz
– 32-bit bus interface brings 64-bit power to 32-bit system cost
– 133.5 Million Integer Mul-Accumulate
– 89 MFlops floating-point operations @267MHz
– 133.5 M Mul-Add/second @267MHz
– 89 MFlops @267MHz
– >640,000 dhrystone (2.1)/sec capability @267MHz (352
– 64-bit, 267 MHz integer CPU
– 8KB instruction cache; 8KB data cache
– Integer multiply unit with 133.5M Mul-Add/sec
High-performance embedded 64-bit microprocessor
High-performance DSP capability
High-performance microprocessor
High level of integration
Upwardly software compatible with IDT RISController
Family
Easily upgradable to 64-bit system
operating frequencies
operations/sec @267MHz
dhrystone MIPS)
267 MHz 64-bit CPU
64-bit Register File
High-Performance
Integer Multiply
Load Aligner
Store Aligner
64-bit Adder
Logic Unit
Instruction Cache
Instruction Cache
(Lockable)
Set A
Set B
Low-Cost Embedded
64-bit RISController
w/ DSP Capability
Instruction Bus
Control Bus
System Control Coprocessor
Cache Attribute Control
Exception Management
Address Translation/
System Interface
1 of 23
Functions
Synchronized
32-bit
– Active power management powers-down inactive units
– Standby mode
– Separate 8KB Instruction and 8KB Data caches
– Over 3200MB/sec bandwidth from internal caches
– 2-set associative
– Write-back and write-through support
– Cache locking, to facilitate deterministic response
– High performance write protocols, for graphics and data
– System interfaces to 125MHz, provides bandwidth up to 500
– Direct interface to 32-bit wide systems
– Synchronized to external reference clock for multi- master
– Socket compatible with IDT RC 64474 and RC64574
– Fast interrupt decode
– Optional cache locking
Low-power operation
Large, efficient on-chip caches
Bus compatible with RC4000 family
Improved real-time support
Data Bus
Note: “R” refers to 5V parts; “RV” refers to 3.3V parts; “RC”
refers to both
communications
MB/sec
operation
89 MFlops Single-Precision FPA
Data Cache
Data Cache
(Lockable)
Set B
Set A
FP Add/Sub/Cvt/
FP Register File
Pack/Unpack
FP Multiply
Div/Sqrt
IDT79RC4640
April 10, 2001
DSC 3486/2

Related parts for IDT79RV4640-133MU

IDT79RV4640-133MU Summary of contents

Page 1

... Integer Multiply Instruction Cache Set A (Lockable) Instruction Cache Set B The IDT logo is a registered trademark and RC4600, RC4650, RC3081,RC3052,RC3051,RC3041 RISController, and RISCore are trademarks of Integrated Device Technology, Inc. 2001 Integrated Device Technology, Inc. Low-Cost Embedded 64-bit RISController w/ DSP Capability Low-power operation – ...

Page 2

IDT79RC4640™ Description Description Description Description The IDT79RC4640 is a low-cost member of the Integrated Device Technology, Inc. RC4000 family, targeted to a variety of performance- hungry embedded applications. The RC4640 continues the RC4000 tradition of high-performance through high-speed pipelines, high-band- ...

Page 3

IDT79RC4640™ The MIPS-III architecture defines that the results of a multiply or divide operation are placed in the HI and LO registers. The values can then be transferred to the general purpose register file using the MFHI/ MFLO instructions. The ...

Page 4

IDT79RC4640™ System Control Coprocessor (CP0) System Control Coprocessor (CP0) System Control Coprocessor (CP0) System Control Coprocessor (CP0) The system control coprocessor in the MIPS architecture is respon- sible for the virtual to physical address translation and cache protocols, the exception ...

Page 5

IDT79RC4640™ address is “in bounds”, the value of the corresponding “base” register is added to the virtual address to form the physical address for that refer- ence. If the address is not within bounds, an exception is signalled. This facility ...

Page 6

IDT79RC4640™ tents will be updated, and the cache line marked for later write- back. If the cache lookup misses, the target line is first brought into the cache before the cache is updated. Write-through with write allocate. Loads and instruction ...

Page 7

IDT79RC4640™ Boot-Time Options Boot-Time Options Boot-Time Options Boot-Time Options ExtRqst* and Release* are used to transfer control of the SysAD and SysCmd buses between the processor and an external device. When an external device needs to control the interface, it ...

Page 8

IDT79RC4640™ If the conditions are not correct when the WAIT instruction finishes the W pipe-stage (i.e. the SysAd bus is not idle), the WAIT is treated as a NOP. Once the CPU is in Standby Mode, any interrupt, including the ...

Page 9

IDT79RC4640™ Data Sheet Revision History Data Sheet Revision History Data Sheet Revision History Data Sheet Revision History Changes to version dated December 1995: Changes to version dated December 1995: Changes to version dated December 1995: Changes to version dated December ...

Page 10

IDT79RC4640™ Mode bit Description 0 Reserved (must be zero) 4s:1 Writeback data rate: 32-bit 0 1 WWx 2 WWxx 3 WxWx 4 WWxxx 5 WWxxxx 6 WxxWxx 7 WWxxxxxx 8 WxxxWxxx 9-15 reserved 7:5 Clock multiplier ...

Page 11

IDT79RC4640™ Pin Description Pin Description Pin Description Pin Description The following is a list of interface, interrupt, and miscellaneous pins available on the RC4640. Pin names ending with an asterisk (*) identify pins that are active when low. Pin Type ...

Page 12

IDT79RC4640™ Pin Type Name ColdReset* Input Cold reset This signal must be asserted for a power on reset or a cold reset. ColdReset must be de-asserted synchronously with MasterClock. Reset* Input Reset This signal must be asserted for any reset ...

Page 13

IDT79RC4640™ DC Electrical Characteristics — Commercial Temperature Range—R4640 DC Electrical Characteristics — Commercial Temperature Range—R4640 DC Electrical Characteristics — Commercial Temperature Range—R4640 DC Electrical Characteristics — Commercial Temperature Range—R4640 ( + 5.0 ...

Page 14

IDT79RC4640™ AC Electrical Characteristics — Commercial Temperature Range—R4640 AC Electrical Characteristics — Commercial Temperature Range—R4640 AC Electrical Characteristics — Commercial Temperature Range—R4640 AC Electrical Characteristics — Commercial Temperature Range—R4640 (V =5. ...

Page 15

IDT79RC4640™ Boot-time Interface Parameters—R4640 Boot-time Interface Parameters—R4640 Boot-time Interface Parameters—R4640 Boot-time Interface Parameters—R4640 (V =5. CASE Parameter Symbol Mode Data Setup t DS Mode Data Hold t DH Capacitive Load Deration—R4650 ...

Page 16

IDT79RC4640™ Power Consumption—RV4640 Power Consumption—RV4640 Power Consumption—RV4640 Power Consumption—RV4640 Parameter Typical System Condition 133/67MHz I standby — CC — active, 400 mA 64-bit bus 450 mA option 500 mA 1. Typical integer instruction mix and cache miss rates, Vcc = ...

Page 17

IDT79RC4640™ AC Electrical Characteristics — Commercial/Industrial Temperature Range— AC Electrical Characteristics — Commercial/Industrial Temperature Range— AC Electrical Characteristics — Commercial/Industrial Temperature Range— AC Electrical Characteristics — Commercial/Industrial Temperature Range— RV4640 RV4640 RV4640 RV4640 (V =3.3V 5%; Commercial T CC CASE ...

Page 18

IDT79RC4640™ System Interface Parameters—RV4640 System Interface Parameters—RV4640 System Interface Parameters—RV4640 System Interface Parameters—RV4640 (V =3.3V 5%; Commercial T CC CASE Note: Timings are measured from 1.5V of the clock to 1.5V of the signal. Parameter 1 Data Output Data Output ...

Page 19

IDT79RC4640™ Timing Characteristics—RV4640 Timing Characteristics—RV4640 Timing Characteristics—RV4640 Timing Characteristics—RV4640 Cycle MasterClock SysAD,SysCmd Driven SysADC SysAD,SysCmd Received SysADC Control Signal CPU driven ValidOut* Release* Control Signal CPU received RdRdy* WrRdy* ExtRqst* ValidIn* NMI* Int*(5: active low signal 1 2 ...

Page 20

IDT79RC4640™ Mode Configuration Interface Reset Sequence Mode Configuration Interface Reset Sequence Mode Configuration Interface Reset Sequence Mode Configuration Interface Reset Sequence Vcc MasterClock (MClk) VCCOK ModeClock ModeIn ColdReset* Reset* Vcc Master Clock (MClk) TDS VCCOK ModeClock ModeIn TDS ColdReset* TDS ...

Page 21

... CHECKED 27.79 (.80 LD PITCH, GULLWING) .80 BSC SCALE .20 REF N/A .89 REF - Integrated Device Technology, Inc. 3001 Stender Way, Santa Clara, CA 95054 dt (408) 492-8333 FAX (408) 727-2328 R SIZE DRAWING NO. A PSC-4054 NOT SCALE DRAWING SHEET OF A1 REV 00 April 10, 2001 ...

Page 22

IDT79RC4640™ RC4640 Package Pin-Out RC4640 Package Pin-Out RC4640 Package Pin-Out RC4640 Package Pin-Out N.C. pins should be left floating for maximum flexibility as well as for compatibility with future designs. An asterisk (*) identifies a pin that is active when ...

Page 23

... Valid Combinations Valid Combinations Valid Combinations Valid Combinations IDT79R4640 - 100, 133MHz - DZ IDT79RV4640 - 133, 150, 180, 200, 267MHz - DU IDT79RV4640 - 133, 150, 180, 200MHz - DUI CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 The IDT logo is a registered trademark of Integrated Device Technology, Inc. ...

Related keywords