MC68160 Motorola, MC68160 Datasheet
MC68160
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MC68160 Summary of contents
Page 1
... Enhanced Ethernet Transceiver The MC68160, B and C Enhanced Ethernet Interface Circuit is a BiCMOS device which supports both IEEE 802.3* Access Unit Interface (AUI) and 10BASE–T Twisted Pair (TP) Interface media connections through external isolation transformers. It encodes NRZ data to Manchester data and supplies the signals which are required for data communication via 10BASE– ...
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... MC68160 MC68160B MC68160C Figure 1. 10Base–T Interface Block Diagram RX Manchester RCLK Decoder MFILT Pulse Conditioner RXLED Carrier RENA Detect CLLED Pulse Conditioner CLSN Mux Pulse TXLED Conditioner TENA Manchester TX Encoder Mux X1 20 MHz X2 Osc TCLK 2 CS0 Jabber CS1 Pre–emphasis Control ...
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... MC68160 MC68160B MC68160C Enhanced Ethernet Serial Transceiver Table 1. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... RCLK. In the standby mode, RENA is driven to the high impedance state. Receive Data Output: Recovered data, synchronous to RCLK. Following a reset operation, 100 ms should be allowed before attempting to read data processed by the MC68160, B and C. This delay is needed to insure that the receive phase locked loop is properly synchronized with incoming data ...
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... Automatic Port Selection Enable: When high, MC68160, B and C will automatically select the TP or AUI port based on the presence or absence of valid link beats or frames at the TP receive input. If the AUI port is automatically selected, the MC68160, B and C will continue to produce link pulses for the TP port. Changing ports requires approximately 1 allow the circuitry for the new port to resume normal operation ...
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... Twisted Pair Receiver Inputs (TPRX+, TPRX–) are reversed, TPPLR will be driven to the low logic state to indicate the fault. TPPLR remains low when the MC68160, B and C has automatically corrected for the reversed wires. If the twisted pair link integrity tests fail, this output will be driven to the high logic state ...
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... CS0 CS1 CS2 NOTE: In standby mode, the MC68160 consumes less power supply current than in any other mode. Additionally, in the standby mode, all of the controller inputs and outputs are driven to the high impedance state. When the standby mode is deasserted, an internal reset pulse of approximately 6.0 s duration is generated. ...
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... Power Supply Voltage Range Power Supply Ripple (20 kHz to 100 kHz) Power Supply Impulse Noise (Either Polarity) Ambient Operating Temperature Range (MC68160, MC68160C) Ambient Operating Temperature Range (MC68160B) ARX/ACX Input Differential Rise and Fall Time (see Figure 39) ARX Pair Idle Time after Transmission (see Figure 39) ...
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... MC68160 MC68160B MC68160C DC ELECTRICAL CHARACTERISTICS limits apply over the recommended ambient operating temperature and power supply voltage ranges for each MC68160 except where noted.) Characteristic TTL COMPATIBLE INPUTS TTL Compatible Input Voltage Low State High State Input Current TTL Compatible Input Pins (Note 1) Input Current TENA TTL Compatible Input Pin: with Pull– ...
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... MC68160 MC68160B MC68160C DC ELECTRICAL CHARACTERISTICS limits apply over the recommended ambient operating temperature and power supply voltage ranges for each MC68160 except where noted.) Characteristic TWISTED PAIR TRANSMITTER OUTPUTS Differential Output Voltage IDLE Mode Open Circuit Differential Output Impedance TRANSMISSION Mode ...
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... MC68160 MC68160B MC68160C Figure 3. Test Load B1 39 Device V1 RCM 1 Device NOTE: A total of 50 per driver output is required for proper series line termination. This is realized with the 39 external resistors shown in Figures 3, 4 and 5, together with the internal driver output resistance. Figure 6. AUI Common Mode Termination ...
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... MC68160 MC68160B MC68160C AC ELECTRICAL CHARACTERISTICS temperature and power supply voltage ranges for each MC68160 except where noted.) Characteristic EXTERNAL CLOCK INPUT (X1) Cycle Time (Note 1) (See Figure 8) Fall Time Rise Time Low Time High Time RECEIVE PHASE–LOCKED–LOOP SWITCHING Stabilization Time ...
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... MC68160 MC68160B MC68160C Figure 9. Receive Phase–Locked–Loop Switching D D CS0 CS1 CS2 1.5V TPRX RENA NOTE: CS0 CS1 CS2 is the logical AND operation and refers to the pins not at Logic 1. Figure 10. Transmit Timing (Motorola Mode 1.5V 1.5V TCLK 1.5V TENA TX Figure 11. Receive Timing (Motorola Start of Frame) 1 ...
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... MC68160 MC68160B MC68160C Figure 12. Receive Timing (Motorola End of Frame) RENA RCLK RX CONTROLLER TRANSMIT SWITCHING (Intel Mode – Support by MC68160 Only) Characteristic TXC Cycle Time TXC High and Low Time TXC Rise and Fall Time TXD Setup Time to TXC TXD Hold Time to TXC ...
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... MC68160 MC68160B MC68160C CRS RXC RXD CONTROLLER TRANSMIT SWITCHING (Fujitsu Mode – Supported by MC68160 Only) Characteristic TCKN Cycle Time TCKN High and Low Time TCKN Rise and Fall Time TXD Setup Time to TCKN TXD Hold Time to TCKN TEN Setup Time to TCKN ...
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... RCKN RXD Figure 17. Receive Timing (Fujitsu End of Frame) XCD RCKN RXD CONTROLLER TRANSMIT SWITCHING (National Mode – Supported by MC68160 Only) Characteristic TXC Cycle Time TXC High and Low Time TXC Rise and Fall Time TXD Setup Time to TXC TXD Hold Time to TXC ...
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... MC68160 MC68160B MC68160C t 111 1.5V TXC t 115 1.5V TXE TXD 1.5V CRS t 125 1.5V RXC RXD MOTOROLA ANALOG IC DEVICE DATA Figure 18. Transmit Timing (National) t 110 3V 1.5V 1.5V 0.8V 0.8V t 111 t 112 t 112 t 113 t 114 1.5V 1.5V Figure 19. Receive Timing (National) t 122 t 120 3V 1.5V 0.8V 1.5V t 121 t 123 t 123 t 124.1 t 124 1.5V t 116 1.5V 1.5V t 126 t 127 1 ...
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... Motorola Mode (MC68160B) Fujitsu Mode (MC68160 Only) National Mode (MC68160 Only) Intel Mode (Note 4) (See Figure 26) (MC68160 Only) TPTX Data–to–Link Test Pulse (Note 2) (See Figure 27) TPTX Link Test Pulse Width (Note 2) TPTX Link Test Pulse Decay–to–Idle Condition (Note 1) TPTX Link Test Pulse to next Link Test Pulse (Note 2) NOTES: 1. Measured differentially across the output of Test Load A which is connected directly to the TPTX+/– ...
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... MC68160 MC68160B MC68160C Figure 24. TPTX Transmit Timing (Start of Frame) Switching X1 TCLK 1.5V TENA 1 TX 1.5V RENA RX TPTX +/– Differential (Logic Levels) TPTX +/– Differential (Pre–Emphasis) Figure 25. TPTX Transmit Timing (End of Frame) Switching t 136 90% TPTX +/– Differential Figure 26. RENA Deassert Delay from TENA ...
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... MC68160 MC68160B MC68160C t 140 t 139 585mV TP TRANSMIT JABBER SWITCHING Characteristic Max Length of Transmission before Assertion of TPJABB to indicate Jabber Condition CLSN to indicate Jabber Condition Time from End of Jabber Condition to Deassertion: of TPJABB of CLSN TP TRANSMIT SIGNAL QUALITY ERROR TEST SWITCHING CLSN (Signal Quality Error Test) (See Figure 29) ...
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... TPRX held high from last valid positive transition (See Figure 33) RENA Deassertion Delay from last valid positive transition of TPRX Pair (MC68160, MC68160C) (See Figure 33) RENA Deassertion Delay from last valid positive transition of TPRX Pair (MC68160B) TP RECEIVE LINK INTEGRITY SWITCHING Required Pulse Width Range to be recognized as a Link Pulse (Note 2) ...
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... MC68160 MC68160B MC68160C Figure 32. TPRX Receive Timing (Start of Frame –300mV TPRX+/– RENA RCLK RX Figure 33. RENA Deassertion Delay from Last Valid Positive Transition of TPRX Pair TPRX+/– RENA Figure 34. TP Receive Link Integrity Switching t 201 TPRX TPLIL 22 Bit n Bit n+1 Bit n+2 ...
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... MC68160 MC68160B MC68160C TP COLLISION SWITCHING Characteristic Time from collision (TPRX activity caused assertion of RENA followed by assertion of TENA) to assertion of CLSN Time from end of collision (Deassertion of TENA with uninterrupted TPRX pair activity) to deassertion of CLSN TP FULL DUPLEX SWITCHING TPFULDL assert to collision detect disable (See Figure 36) ...
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... MC68160 MC68160B MC68160C AUI TRANSMIT SWITCHING Characteristic TCLK to ATX Pair Steady State Propagation Delay Output Differential Rise and Fall Times (Measured directly at device pins) ATX Bit Cell Duration center–to–center (Measured directly at device pins) ATX Half–Bit Cell Duration center–to–boundary (Measured directly at device pins) ...
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... All but one are open collector outputs. If the EEST isn’t receiving data, the controller may initiate transmission. NRZ data from the communications controller SIA interface is encoded by the MC68160 into Manchester Code in preparation for transmission on the media. The data is then applied to either the AUI or TP port. ...
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... MC68160, B and C Manchester encode and decode function. LOOP must not be asserted when TPFULDL pin is asserted. This causes the MC68160, B and C to enter a test mode. This test mode is used during final test and is not intended to be entered under normal operation (see Application Notes section) ...
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... TPSQEL low, raise LOOP after 300 ms lower TPFULDL. This C5) will put the MC68160 into test mode but also resets the MC68160. After 500 ms lower LOOP to get out of the test mode. TPFULDL may then be de–asserted if desired. The MC68160 is now ready for operation. ...
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... MC68160 MC68160B MC68160C Figure 41. Î Î Î Î Î Î PE-65424) Î Î Î Î Î Î Î Î Î Î Î Î TXLED RXLED CLLED TPLIL TPPLR TPJABB TPEN GNDCTL TCLK TENA RCLK CLSN (Example ATX+ ATX– ARX+ ARX– ...
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... MC68160 MC68160B MC68160C 4X 0.20 (0.008) H L– VIEW Y 3X –L– –N– –H– –T– 3 SEATING 4X PLANE 0.05 (0.002 VIEW AA MOTOROLA ANALOG IC DEVICE DATA OUTLINE DIMENSIONS FB SUFFIX PLASTIC PACKAGE CASE 848D-03 (TQFP–52) ISSUE C 4X TIPS 0.20 (0.008) T L– ...
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... MC68160 MC68160B MC68160C Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “ ...