AM79C971 Advanced Micro Devices, AM79C971 Datasheet
AM79C971
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AM79C971 Summary of contents
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... Am79C971 PCnet™-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus DISTINCTIVE CHARACTERISTICS Single-chip Fast Ethernet controller for the Peripheral Component Interconnect (PCI) local bus — 32-bit glueless PCI host interface — Supports PCI clock frequency from MHz independent of network clock — ...
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... Ethernet Capture Effect IEEE 1149.1-compliant JTAG Boundary Scan test access port interface and NAND tree test GENERAL DESCRIPTION The Am79C971 controller is a single-chip 32-bit full-du- plex, 10/100-Megabit per second (Mbps) highly- integrated Ethernet system solution, designed to address high-performance system application require- ments ...
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... SRAM interface provides high performance and high latency tolerance on the system bus and net- work. The Am79C971 controller can use up to 128 Kbytes of SRAM as an extension of its dual Transmit and Receive FIFOs. When no SRAM is used, the Am79C971 con- troller’s FIFOs are programmed to bypass the SRAM interface. IMPORTANT NOTE: A “ ...
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... Am79C971 Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local KC\W, AMD sales office to confirm availability of specific VC\W valid combinations and to check on newly released combinations. Am79C971 ...
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... Xmt Xmt FIFO FIFO Manchester Encoder/ Network Decoder Port (PLS) & Manager AUI Port FIFO 10BASE-T Control Auto Negotiation EEPROM Interface Am79C971 TXEN TXCLK TXDAT GPSI RXEN Port RXCLK RXDAT CLSN TX_E TXD[3:0] TX_EN TX_CLK COL MII RXD[3:0] Port RX_ER RX_CLK ...
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... TABLE OF CONTENTS AM79C971 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Standard Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 BLOCK DIAGRAM RELATED AMD PRODUCTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 CONNECTION DIAGRAM (PQR160 .11 CONNECTION DIAGRAM (PQL176 .12 PIN DESIGNATIONS (PQR160 .13 Listed By Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 PIN DESIGNATIONS (PQL176 .14 Listed By Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 PIN DESIGNATIONS (PQR160, PQL176 .15 Listed By Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 PIN DESIGNATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Listed By Group ...
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... MIIRXFRTGD .27 MIIRXFRTGE .27 IEEE 1149.1 (1990) Test Access Port Interface .28 TCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 TDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 TDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 TMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 AVDDB .28 AVSSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 VDD_PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 VSS_PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 VDDB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 VSSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 VDD_PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 BASIC FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 System Bus Interface .29 Software Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Network Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 DETAILED FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Slave Bus Interface Unit .30 Am79C971 7 ...
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... REGISTER SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190 PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191 Bus Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195 REGISTER PROGRAMMING SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196 Am79C971 Programmable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES UNLESS OTHERWISE SPECIFIED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 SWITCHING CHARACTERISTICS: BUS INTERFACE .203 SWITCHING CHARACTERISTICS: 10BASE-T INTERFACE ...
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... PHYSICAL DIMENSIONS .229 PQR160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229 PQL176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230 AM79C971 COMPATIBLE MEDIA INTERFACE MODULES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-1 RECOMMENDATION FOR POWER AND GROUND DECOUPLING .B-1 ALTERNATIVE METHOD FOR INITIALIZATION .C-1 LOOK-AHEAD PACKET PROCESSING (LAPP) CONCEPT .D-1 AUTO-NEGOTIATION REGISTERS ...
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... PCnet-ISA II Single-Chip Full-Duplex Ethernet Controller (with Microsoft® Plug n' Play support) Am79C965 PCnet-32 Single-Chip 32-Bit Ethernet Controller (for 486 and VL buses) Am79C970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Am79C981 Integrated Multiport Repeater Plus™ (IMR+™) Am79C987 Hardware Implemented Management Information Base™ (HIMIB™) 10 Am79C971 ...
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... AD11 31 AD10 32 VDD 33 AD9 34 AD8 35 VSS 36 C/BE0 37 AD7 38 AD6 39 VSSB 40 Pin 1 is marked for orientation. PCnet™- FAST Am79C971 KC/W Am79C971 Am79C971 XTAL2 120 VSS_PLL 119 118 XTAL1 117 AVDDB 116 TXD+ 115 TXP+ TXD- 114 TXP- 113 112 AVDDB 111 RXD+ ...
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... AD10 35 VDD 36 AD9 37 AD8 38 VSS 39 C/BE0 40 AD7 41 AD6 42 VSSB Pin 1 is marked for orientation. 12 PCnetª- FAST Am79C971 VC/W VC/W Am79C971 Am79C971 132 NC 131 NC 130 XTAL2 VSS_PLL 129 XTAL1 128 127 AVDDB 126 TXD+ 125 TXP+ TXD- 124 123 TXP- 122 ...
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... TXD- 154 115 TXP+ 155 116 TXD+ 156 117 AVDDB 157 118 XTAL1 158 119 VSS_PLL 159 120 XTAL2 160 Am79C971 Pin Name AVSSB DO- DO+ AVDDB DI- DI+ CI- CI+ VDD_PLL VDDB EEDO/LED3/SRD/ MIIRXFRTGD EED1/LED0 LED2/SRDCLK/ MIIRXFRTGE EESK/LED1/SFBD VSSB EECS TCK ...
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... TXP+ 169 126 TXD+ 170 127 AVDDB 171 128 XTAL1 172 129 VSS_PLL 173 130 XTAL2 174 131 NC 175 132 NC 176 Am79C971 Pin Name NC NC AVSSB DO- DO+ AVDDB DI- DI+ CI- CI+ VDD_PLL VDDB EEDO/LED3/SRD/ MIIRXFRTGD EED1/LED0 LED2/SRDCLK/ MIIRXFRTGE EESK/LED1/SFBD VSSB EECS TCK ...
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... Type Driver Am79C971 No. of Pins TS3 32 TS3 STS6 1 STS6 OD6 1 STS6 1 TS3 1 STS6 1 TS3 OD6 1 STS6 1 STS6 1 LED 1 LED 1 LED ...
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... Type Driver Am79C971 No. of Pins OMII2 1 TSMII OMII1 4 OMII1 1 OMII1 TDO 2 TPO 2 NA ...
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... PCI I/O Buffer Power Note: 1. Not including test features. Listed By Driver Type The following table describes the various types of out- put drivers used in the Am79C971 controller. All I I values shown in the table apply signaling. OH See the DC Characteristics section for the values ap- plying to 3 ...
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... When RST is active, GNT is an input for NAND tree testing. IDSEL Initialization Device Select Input This signal is used as a chip select for the Am79C971 controller during configuration read and write transac- tions. When RST is active, IDSEL is an input for NAND tree testing. ...
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... IRDY and TRDY are asserted simultaneously. A data phase is completed on any clock when both IRDY CSR4, bit 9 and TRDY are asserted. When the Am79C971 controller is a bus master, it as- CSR5, bit 4 serts IRDY during all write data phases to indicate that valid data is present on AD[31:0]. During all read data ...
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... AD[31:0]. During all write data phases, the device checks TRDY to determine if the target is ready to accept the data. When the Am79C971 controller is the target of a trans- action, it asserts TRDY during all read data phases to indicate that valid data is present on AD[31:0]. During all write data phases, the device asserts TRDY to indi- cate that it is ready to accept the data ...
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... All Am79C971 controller inputs will be ignored except for the SLEEP pin itself. The sys- tem must refrain from starting the network operations of the Am79C971 controller for 0.5 seconds following the deassertion of the SLEEP pin in order to allow in- ternal analog circuits to stabilize. ...
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... This pin is designed to directly interface to a serial EEPROM that uses the 93C46 EEPROM interface pro- tocol. EESK is connected to the EEPROM’s clock pin controlled by either the Am79C971 controller di- rectly during a read of the entire EEPROM, or indirectly Output by the host system by writing to BCR19, bit 1. ...
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... TX_CLK Transmit Clock TX_CLK is a continuous clock input that provides the timing reference for the transfer of the TX_EN, TXD[3:0], and TX_ER signals out of the Am79C971 device. TX_CLK must provide a nibble rate clock (25% of the network data rate). Hence, an MII transceiver op- Output erating at 10 Mbps must provide a TX_CLK frequency of 2 ...
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... RXD[3:0] pins and RX_CLK is synchronous to the receive data. In order Input for a frame to be fully received by the Am79C971 de- vice on the MII, RX_DV must be asserted prior to the RX_CLK rising edge, when the first nibble of the Start of Frame Delimiter is driven on RXD[3:0], and must re- main asserted until after the rising edge of RX_CLK, when the last nibble of the CRC is driven on RXD[3:0] ...
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... CI operates at pseudo ECL levels. If the CI pins are not used, they should be tied to- gether. DI Data differential input pair to the Am79C971 control- ler carrying Manchester encoded data from the net- work. DI operates at pseudo ECL levels. If the DI pins are not used, they should be tied to- gether. DO ...
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... RXD[3:0] pins. SFBD will go high for one nibble time (400 ns when op- erating at 10 Mbps and 40 ns when operating at 100 Mbps) one RX_CLK period after RX_DV has been as- serted and RX_ER is deasserted and the detection of Am79C971 Output Input Output ...
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... Receive Frame Tagging is enabled (RXFRTG, CSR7, bit 14), and the MII is selected, the MIIRXFRTGE pin becomes a data input enable pin for the Receive Frame Tag. See the Receive Frame Tagging section for de- tails. Note: The MIIRXFRTGE pin is multiplexed with the SRDCLK pin. Am79C971 Input Input Input/Output Input/Output 27 ...
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... It can operate at a frequency MHz. TCK has an internal pull up resistor. TDI Test Data In TDI is the test data input path to the Am79C971 con- troller. The pin has an internal pull up resistor. TDO Test Data Out TDO is the test data output path from the Am79C971 controller ...
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... While in auto-selection mode, the interface in use is de- termined by the Network Port Manager. If the quiescent state of the MII MDIO pin is HIGH, the MII is activated. If the MII MDIO pin is LOW, the Am79C971 device checks the link status on the 10BASE-T port. If the 10BASE-T link status is good, the 10BASE-T port is se- lected ...
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... PCI configuration space, the Control and Status Registers (CSR), the Bus Configuration Registers (BCR), the Address PROM (APROM) locations, and the Expansion ROM. Table 2 shows the response of the Am79C971 controller to each of the PCI commands in slave mode. Table 2. Slave Commands C[3:0] Command ...
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... The typical number of wait states added to a slave I/O or memory mapped I/O read or write access on the part of the Am79C971 controller is six to seven clock cycles, depending upon the relative phases of the internal Buffer Management Unit clock and the CLK signal, since the internal Buffer Management Unit clock is a di- vide-by-two version of the CLK signal ...
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... STOP Figure 3. CLK 1 FRAME ADDR AD 0011 C/BE PAR IRDY TRDY DEVSEL STOP Figure 4. Slave Write Using Memory Command PAR Slave Read Using I/O Command DATA BE PAR PAR Am79C971 DATA PAR 20550D 20550D-7 ...
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... The host must initialize the Expansion ROM Base Ad- dress register at offset 30H in the PCI configuration space with a valid address before enabling the access to the device. The Am79C971 controller will not react to any access to the Expansion ROM until both MEMEN (PCI Command register, bit 1) and ROMEN (PCI Ex- pansion ROM Base Address register, bit 0) are set to 1 ...
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... ROM detection fails by connecting two adjacent EBD pins together. Slave Cycle Termination There are three scenarios besides normal completion of a transaction where the Am79C971controller is the target of a slave cycle and it will terminate the access. Disconnect When Busy The Am79C971controller cannot service any slave ac- cess while it is reading the contents of the EEPROM ...
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... If the host is not yet ready when the Am79C971 control- ler asserts TRDY, the device will wait for the host to as- sert IRDY. When the host asserts IRDY and FRAME is still asserted, the Am79C971controller will finish the first data phase by deasserting TRDY one clock later. ...
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... Bus Acquisition The Am79C971microcode will determine when a DMA transfer should be initiated. The first step in any Am79C971bus master transfer is to acquire ownership of the bus. This task is handled by synchronous logic within the BIU. Bus ownership is requested with the REQ signal and ownership is granted by the arbiter through the GNT signal ...
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... Basic Non-Burst Read Transfer By default, the Am79C971 controller uses non-burst cycles in all bus master read operations. All Am79C971 controller non-burst read accesses are of the PCI command type Memory Read (type 6). Note that during a non-burst read operation, all byte lanes will always be active ...
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... Figure 13. Burst Read Transfer (EXTREQ = 0, MEMCMD = DATA ADDR ADDR 0110 0110 0000 PAR PAR PAR Figure 12. Non-Burst Read Transfer ADDR DATA DATA 1110 0000 PAR PAR Am79C971 DATA 0000 PAR 20550D- DATA PAR PAR 20550D-16 ...
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... BWRITE (BCR18, bit 5). To allow burst transfers in descriptor write operations, the Am79C971 controller must also be programmed to use SWSTYLE 3 (BCR20, bits 7-0). All Am79C971 control- ler burst write transfers are of the PCI command type Memory Write (type 7). AD[1:0] will both be 0 during the address phase indicating a linear burst order ...
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... EXTREQ (BCR18, bit 8) is set to 1, therefore, REQ is not deasserted until the next to last data phase is fin- ished. Target Initiated Termination When the Am79C971 controller is a bus master, the cy- cles it produces on the PCI bus may be terminated by the target in one of three different ways. CLK ...
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... It finally releases the bus on clock 6. Since data integrity is not guaranteed, the Am79C971 controller cannot recover from a target abort event. The Am79C971 controller will reset all CSR locations to their STOP_RESET values. The BCR and PCI config- uration registers will not be cleared. Any on-going net- wor k transmission is ter minated in an order ly sequence ...
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... Preemption During Non-Burst Transaction When the Am79C971 controller performs multiple non- burst transactions, it keeps REQ asserted until the as- sertion of FRAME for the last transaction. When GNT is removed, the Am79C971 controller will finish the cur- rent transaction and then release the bus not the 42 2 ...
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... When it sees the PERR input asserted, the controller sets PERR (PCI Status register, bit 15 When PERREN (PCI Command register, bit 6) is set to 1, the Am79C971 controller also sets DATAPERR (PCI Status register, bit Am79C971 ...
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... GNT Figure 20. Preemption During Burst Transaction 44 CLK ADDR DATA 0111 BE PAR PAR PAR DEVSEL is sampled ADDR DATA DATA DATA DATA 0111 BE PAR PAR PAR PAR DEVSEL is sampled Am79C971 6 7 20550D- DATA PAR PAR 20550D-23 ...
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... DEVSEL REQ GNT DEVSEL is sampled Figure 21. Master Abort CLK FRAME AD ADDR 0111 C/BE BE PAR PAR PERR IRDY TRDY DEVSEL DEVSEL is sampled Figure 22. Master Cycle Data Parity Error Response Am79C971 DATA 0000 PAR DATA PAR 20550D-24 20550D-25 45 ...
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... PERREN (PCI Command register, bit 6). By default, a data parity error does not affect the state of the MAC engine. The Am79C971 controller treats the data in all bus master transfers that have a parity error as if nothing has happened. All network activity contin- ues ...
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... During descriptor read accesses, the byte enable sig- nals will indicate that all byte lanes are active. Should some of the bytes not be needed, then the Am79C971 controller will internally discard the extraneous informa- tion that was gathered during such a read. ...
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... Figure 25. Descriptor Ring Read In Non-Burst Mode 48 CLK IADD i DATA DATA 0110 0000 PAR PAR PAR GNT DEVSEL is sampled MD1 DATA MD0 0110 0000 0110 PAR PAR Am79C971 6 7 PAR 20550D- DATA 0000 PAR PAR 20550C-28 ...
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... Every data phase in non-burst and burst mode is extended by one clock cycle, during which IRDY is deasserted. Note that Figure 26 assumes that the Am79C971 con- troller is programmed to use 32-bit software structures (SWSTYLE = 2 or 3). The byte enable signals for the ...
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... FIFO DMA Transfers Am79C971 microcode will determine when a FIFO DMA transfer is required. This transfer mode will be used for transfers of data to and from the Am79C971 FIFOs. Once the Am79C971 BIU has been granted bus mastership, it will perform a series of consecutive transfer cycles before relinquishing the bus. All trans- ...
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... Figure 27. Descriptor Ring Write In Non-Burst Mode CLK FRAME MD2 AD C/BE 0110 0000 PAR PAR IRDY TRDY DEVSEL REQ GNT DEVSEL is sampled Figure 28. Descriptor Ring Write In Burst Mode Am79C971 DATA MD1 0111 0011 PAR PAR DATA DATA 0011 PAR PAR ...
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... When the software ensures that all receive buffers end on a DWord boundary, IWAIT can be set this mode, the Am79C971 controller will only insert a wait state in the first data phase of the burst write transaction. 52 ...
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... CSR2 (most signifi- cant 16 bits of address). The host must write CSR1 and CSR2 before setting the INIT bit. The initialization block contains the user defined conditions for Am79C971 op- eration, together with the base addresses and length information of the transmit and receive descriptor rings. ...
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... H_RESET, S_RESET setting the STOP bit), no re-initialization of the device is required after the device comes out of suspend mode. When SPND is set to 0, the Am79C971 controller will leave the suspend mode and will continue at the transmit and receive descriptor ring locations, where it had been when it entered the suspend mode. See the section on Magic Packet™ ...
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... Am79C971 controller or the host. The OWN bit within the descriptor status information, either TMD or RMD, is used for this purpose. When OWN is set signifies that the Am79C971 controller currently has ownership of this ring descrip- tor and its associated buffer. Only the owner is permit- ted to relinquish ownership or to write to any field in the descriptor entry ...
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... Am79C971 controller does not own the current RDTE and the poll time has elapsed and RXON = 1 (CSR0, bit 5 Am79C971 controller does not own the next RDTE and there is more than one receive descriptor in the ring and the poll time has elapsed and RXON = 1. ...
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... RES LADRF[31:0] LADRF[63:32] RDRA[31:0] TDRA[31:0] If RXON is cleared to 0, the Am79C971 controller will never poll RDTE locations. In order to avoid missing frames, the system should have at least one RDTE available. To minimize poll ac- tivity, two RDTEs should be available. In this case, the poll operation will only consist of the check of the status of the current TDTE ...
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... OWN bit has a 0 value, the Am79C971 controller will resume incrementing the poll time counter. If the trans- mit descriptor OWN bit has a value of 1, the Am79C971 controller will begin filling the FIFO with transmit data and initiate a transmission. This end-of-operation poll ...
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... Counter (CSR112) will be incremented. Another poll of the current RDTE will not occur until the frame has fin- ished. If the Am79C971 controller sees that the last poll (ei- ther a normal poll, or the final effort described in the above paragraph) of the current RDTE shows valid ownership, it proceeds to a poll of the next RDTE ...
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... If the length field has a value greater, all frame bytes including FCS will be passed unmodified to the receive buffer, regardless of the actual frame length. If the frame terminates or suffers a collision before 64 bytes of information (after SFD) have been received, Am79C971 ...
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... MAC engine will automatically delete the frame from the receive FIFO, without host intervention. The Am79C971 controller has the ability to accept runt packets for diagnostic purposes and proprietary net- works. Destination Address Handling The first 6 bytes of information after SFD will be inter- preted as the destination address field ...
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... Am79C971 controller possi- bly capturing the network at times by forcing other less aggressive compliant nodes to defer. By programming a larger number of bit times, the Am79C971 MAC will become less aggressive on the network and may defer more often than normal. The performance of the ...
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... IPG counter will be reset by a worst case IPG shrink- age/fragment scenario and the Am79C971 controller will defer its transmission. If carrier is detected within the 4.0 to 6.0 s IFS1 period, the Am79C971 controller will not restart the “blinding” period, but only restart IFS1. Collision Handling ...
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... Data bytes encapsulated in the frame (length field as defined in the ISO 8802-3 (IEEE/ANSI 802.3) stan- dard). The length value contained in the message is not used by the Am79C971 controller to compute the ac- tual number of pad bytes to be inser ted. The Am79C971 controller will append pad bytes dependent on the actual number of bits transmitted onto the net- work ...
Page 65
... FIFO can be overwritten as soon transmitted total attempts (initial attempt plus 15 retries) fail, the Am79C971 controller sets the RTRY bit in the cur- rent transmit TDTE in host memory (TMD2), gives up ownership (resets the OWN bit to 0) for this frame, and processes the next frame in the transmit ring for trans- mission ...
Page 66
... LAFM (RMD1, bit 21) is set by the Am79C971 control- ler when it accepted the received frame based on the value in the logical address filter register. ...
Page 67
... When the Am79C971 controller is not programmed promiscuous mode, but the EADI interface is en- abled, then when none of the three match bits is set indication that the Am79C971 controller only ac- cepted the frame because it was not rejected by driving the EAR pin LOW within 64 bytes after SFD. ...
Page 68
... Since any valid Ethernet Type field value will always be greater than a normal IEEE 802.3 Length field ( 46), the Am79C971 controller will not attempt to strip valid Ethernet frames. Note that for some network protocols, the value passed in the Ethernet Type and/or IEEE 802.3 Length field is not compliant with either standard and may cause problems if pad stripping is enabled ...
Page 69
... FCS generation or checking testing multicast address detection as they exist in the half-duplex PCnet family devices and in the C-LANCE. On receive, the Am79C971 con- troller now provides true FCS status. The descriptor for a frame with an FCS error will have the FCS bit (RMD1, bit 27) set to 1 ...
Page 70
... The MENDEC contains a Power On Reset (POR) circuit, which ensures that all analog portions of the Am79C971 controller are forced into their correct state during power up, and prevents erroneous data transmission and/or reception during this time. ...
Page 71
... HIGH or change to LOW state whenever IRXCLK is enabled. At 1/4 bit time into bit cell 5, the controller portion of the Am79C971 controller sees the first IRX- CLK transition. This also strobes in the incoming fifth bit to the MENDEC as Manchester 1. IRXDAT may make a transition after the IRXCLK rising edge in bit cell 5, but its state is still undefined ...
Page 72
... Layer Signaling) to PMA (Physical Medium Attach- ment) interface which effectively connects the DTE to a MAU. The differential interface provided by the Am79C971 controller is fully compliant to Section 7 of ISO 8802-3 (ANSI/IEEE 802.3) standard. After the Am79C971 controller initiates a transmission it will expect to see data “looped-back” on the DI pair (when the AUI port is selected). This will internally gen- erate a “ ...
Page 73
... Figure 14-12 of the 10BASE-T Standard, is generated at a transmitter and passed through 100 m of twisted pair cable. Negative link beat pulses are defined as received sig- nals with a negative amplitude greater than 585 mV Am79C971 73 ...
Page 74
... Refer to the PCnet Family Board Design and Layout Recommendations Application Note (PID #19595A) for more design details. Also, refer to Appen- dix A, Am79C971 Compatible Media Interface Modules for a list of compatible 10BASE-T filter/transformer modules. Note: The recommended resistor values and filter and transformer modules are the same as those used by the IMR+ (Am79C981) ...
Page 75
... General Purpose Serial Interface The General Purpose Serial Interface (GPSI) provides a direct interface to the MAC section of the Am79C971 controller. All signals are digital and data is non-en- coded. The GPSI allows use of an external Manchester encoder/decoder such as the Am7992B Serial Inter- face Adapter (SIA). In addition, it allows the Am79C971 ...
Page 76
... MII Receive Interface The MII receive clock is also generated by the external PHY and is sent to the Am79C971 controller on the RX_CLK input pin. The clock will be the same fre- quency as the TX_CLK but will be out of phase and can run at 25 MHz or 2 ...
Page 77
... Am79C971 controller can control and receive status from external PHY devices. . Am79C971 The Am79C971 controller can support exter- nal PHYs attached to the MII Management Interface with software support and only one such device without software support. The Network Port Manager copies the PHYAD after the Am79C971 controller reads the EEPROM and uses it to communicate with the external PHY ...
Page 78
... PHY will drive the external PHY does not drive a 0, the Am79C971 controller will signal a MREINT (CSR7, bit 9) interrupt, if MREINTE (CSR7, bit 8) is set indicating the Am79C971 controller had an MII management frame read error and that the data in BCR34 is not valid. The data field to/from the internal or external PHY is read or written into the BCR34 register ...
Page 79
... MII Status register in the ex- ternal PHY. Network Port Manager The Am79C971 controller is unique in that it does not require software intervention to control and configure an external PHY attached to the MII. This was done to ensure backwards compatibility with existing software drivers ...
Page 80
... PHY is attached to the MII Management Interface, then the DANAS (BCR32, bit 7) bit must be set to 1 and then all configuration control should revert to software. The Am79C971 controller will read the reg- ister of the external PHY to determine its status and network capabilities. See Appendix E, Auto Negotiation Registers, for the bit descriptions of the MII Status reg- ister ...
Page 81
... See Appendix E for the bit descriptions of the MII Status register. If the external PHY is Auto-Negotiation capable and/or the XPHYANE (BCR32, bit 5) bit is set to 1, then the Am79C971 con- troller will start the external PHY’s Auto-Negotiation process. The Am79C971 controller will write to the ex- ternal PHY’ ...
Page 82
... Am79C971 controller or the frame is of the type ’Broadcast’, then the frame will be accepted regardless of the condition of EAR. When the EADISEL bit of BCR2 is set to 1 and the Am79C971 controller is programmed to promiscuous mode (PROM bit of the Mode Register is set to 1), then all in- coming frames will be accepted, regardless of any ac- tivity on the EAR pin ...
Page 83
... The receive frame tagging implementation will be a two- and three-wire chip interface, respectively, added to the existing EADI. The Am79C971 controller supports bits of re- ceive frame tagging per frame in the receive frame sta- tus (RFRTAG). The RFRTAG bits are in the receive frame status field in RMD2 (bits 30-16) in 32-bit soft- ware mode ...
Page 84
... The Am79C971 controller is function- ally equivalent to the PCnet-PCI II controller with Ex- pansion ROM. See Figure 43 and Figure 44. The Am79C971 controller will always read four bytes for every host Expansion ROM read access. The interface to the Expansion Bus runs synchronous to the PCI bus interface clock ...
Page 85
... EBUA_EBA[7:0] Am79C971 Figure 42. SRAM and Flash Configuration for the Expansion Bus The time that the Am79C971 controller waits for data to be valid is programmable. ROMTMG (BCR18, bits 15- 12) defines the time from when the Am79C971 control- ler drives EBUA_EBA[7:0] with the lower 8 bits of the Expansion ROM address to when the Am79C971 con- troller latches in the data on the EBD[7:0] inputs ...
Page 86
... PCI Memory Mapped I/O Base Address register, before enabling access to the Expansion ROM. The host must set the PCI Memory Mapped I/O Base Ad- dress register to a value that prevents the Am79C971 controller from claiming any memory cycles not in- tended for it. During the boot procedure, the system will try to find an Expansion ROM ...
Page 87
... EBD[7:0] Am79C971 EBWE ERAMCS EBUA_EBA[7:0] EROMCS EBDA[15:8] AS_EBOE Figure 44. EPROM Only Configuration for the Expansion Bus (>64K EPROM) '374 D-FF A[19:16] A[15:8] A[7:0] EPROM DQ[7: Am79C971 20550D-47 87 ...
Page 88
... CLK EBUA_EBA[7:0] EBDA[15:8] EBD[7:0] EROMCS AS_EBOE Figure 46. Flash Read from Expansion Bus Data Port 88 Upper Lower Address Address tv_A_D DATA t_CS_L t_WE_L t_AS_H EBUA[19:16 EBA[7:0] EBDA[15:8] Am79C971 Lower Address DATA t_CS_H t_WE_CSAD t_WE_H 20550D- 20550D-49 ...
Page 89
... FLASH devices as long as there is no timing require- ment between the completion of commands. The FLASH access time cannot be guaranteed with the Am79C971 controller access mechanism. The Am79C971 controller will also support only Flash de- vices that do not require data hold times after write op- erations. Am79C971 ...
Page 90
... Expansion Bus. The external SRAM should be programmed on a 512- byte boundary. However, there should be no accesses to the RAM space while the Am79C971 controller is running. The Am79C971 controller assumes that it completely owns the SRAM while operation. To specify how much of the SRAM is allocated to transmit ...
Page 91
... Figure 48. SRAM Only Configuration for the Expansion Bus Expansion Bus Interface Bus Rcv FIFO PCI Bus Interface Unit Bus Xmt FIFO Buffer FIFO Management Control Unit Figure 49. Block Diagram With External SRAM Am79C971 I/O[7:0] A[14:8] A[7:0] 32K x 8 SRAM I/O[7:0] A[14:8] A[7:0] 32K x 8 SRAM MAC Rcv FIFO 802 ...
Page 92
... SRAM is required at all times. If the SRAM_SIZE (BCR25, bits 7-0) value is 0, the Am79C971 controller will not configure for low latency receive mode. The Am79C971 controller will provide a fast path on the re- ceive side bypassing the external RAM. All transmit traffic will go to the SRAM, so SRAM_BND (BCR26, bits 7-0) has no meaning in low latency receive mode ...
Page 93
... This results in the best utilization for the 4-FIFO arbiter in the Am79C971 controller. If the FIFO does not have enough data to complete the full 18 cycles, the arbiter will switch after all of the data has been written or read ...
Page 94
... EEPROM. If the checksum verification passes, PVALID (BCR19, bit 15) will be set the checksum verification of the EEPROM data fails, PVALID will be cleared to 0, and the Am79C971 con- troller will force all EEPROM-programmable BCR reg- isters back to their H_RESET default values. However, ...
Page 95
... At the rising edge of CLK during the last clock dur- ing which RST is asserted, the Am79C971 controller will sample the value of the EESK/LED1/SFBD pin. If the sampled value then the Am79C971 controller assumes that an EEPROM is present, and the EE- PROM read operation begins shortly after the RST pin is deasserted ...
Page 96
... Reserved location must be 00h 32h Reserved location must be 00h 34h Reserved location must be 00h 36h Reserved location must be 00h 38h Reserved location must be 00h 3Ah Reserved location must be 00h 3Ch Reserved location must be 00h 3Eh Reserved location must be 00h Am79C971 Least Significant Byte ...
Page 97
... When an LED circuit is directly connected to the EEDO/LED3/SRD pin, then it is not possible for most EEPROM devices to sink enough I OL low level on the EEDO input to the Am79C971 control- ler. Each LED can be programmed through a BCR register to indicate one or more of the following network status ...
Page 98
... Once the T-MAU has a good link, LED0 will be active. This LED0 pin can be used to drive an LED and/or external hardware that directly controls the SLEEP pin of the Am79C971 controller. In the case of driving external hardware, it can be used to tell an external SLEEP control logic to drive the SLEEP pin HIGH to bring the Am79C971 controller out of the snooze mode ...
Page 99
... Re-initial- ization should not be performed. If the part is re-initial- ized, then the descriptor locations will be reset also, and the Am79C971 controller will not start where it left off. If Magic Packet mode is disabled by the deassertion of SLEEP, then in order to immediately re-enable Magic Packet mode, the SLEEP pin must remain deasserted for at least 200 ns before it is reasserted ...
Page 100
... NAND tree inputs are driven low. See Figure 56. Note: Some of the pins connected to the NAND tree are outputs in normal mode of operation. They must not be driven from an external source until the Am79C971 controller is configured for NAND tree testing. Am79C971 Core ...
Page 101
... C/BE1 26 AD15 28 AD14 29 AD13 29 AD12 31 AD11 32 AD10 34 AD9 35 AD8 37 C/BE0 38 AD7 39 AD6 41 AD5 42 AD4 43 AD3 44 AD2 46 AD1 Am79C971 1 ... 20550D-59 NAND Tree Input No. Pin No. Name 49 47 AD0 50 79 CRS 51 80 COL 52 81 TXD3 53 90 TXD2 54 91 TXD1 55 92 TXD0 56 94 TX_EN 57 95 ...
Page 102
... H_RESET Hardware Reset (H_RESET Am79C971 reset operation that has been created by the proper asser- tion of the RST pin of the Am79C971 device. When the minimum pulse width timing as specified in the RST pin description has been satisfied, then an internal reset operation will be performed. ...
Page 103
... PCI configuration utility after system power-up. The PCI configuration utility must also set the IOEN bit in the PCI Command regis- ter to enable I/O accesses to the Am79C971 controller. For memory mapped I/O access, the PCI Memory Mapped I/O Base Address register controls the start address of the memory space ...
Page 104
... I/O mode is usually the first oper- ation after H_RESET or S_RESET. The RAP register will point to CSR0 at that time. Writing a value CSR0 is a safe operation. DWIO (BCR18, bit 7) will be set indication that the Am79C971 controller operates in 32-bit I/O mode. Am79C971 Register ...
Page 105
... H_RESET or S_RESET. The RAP register will point to CSR0 at that time. Writing a value CSR0 is a safe operation. DWIO (BCR18, bit 7) will be set indication that the Am79C971 controller operates in 32-bit I/O mode. The DWIO mode can be configured from the EEPROM or programmed by the software ...
Page 106
... DWord write to RDP, switches device to DWord I/O mode USER ACCESSIBLE REGISTERS Register The Am79C971 controller has three types of user reg- isters: the PCI configuration registers, the Control and Status registers (CSR), and the Bus Control registers (BCR). The Am79C971 controller implements all PCnet-ISA (Am79C960) registers, all C-LANCE (Am79C90) regis- ters, plus a number of additional registers ...
Page 107
... Am79C971 controller features. The following is a list of the registers that would typi- cally need to be programmed once during the setup of the Am79C971 controller within a system. The control bits in each of these registers typically do not need to be modified once they have been written. However, there are no restrictions as to how many times these registers may actually be accessed ...
Page 108
... Am79C971 con- troller. It controls the Am79C971 controller's ability to generate and respond to PCI bus cycles. To logically disconnect the Am79C971 device from all PCI bus cy- cles except configuration cycles, a value of 0 should be written to this register. The PCI Command register is located at offset 04h in the PCI Configuration Space ...
Page 109
... S_RESET or by setting the STOP bit. 1 MEMEN Memory Space Access Enable. The Am79C971 controller will ig- nore all memory accesses when MEMEN is cleared. The host must set MEMEN before the first memory access to the device. For memory mapped I/O, the ...
Page 110
... PERR signal. PERR is not effected by the state of the Parity Error Response en- able bit (PCI Command register, bit 6). PERR is set by the Am79C971 controller and cleared by writing a 1. Writing a 0 has no effect. PERR is cleared by H_RESET and is not affected by S_RESET or by setting the STOP bit. ...
Page 111
... PCI I/O Base Address Register Offset 10h The PCI I/O Base Address register is a 32-bit register that determines the location of the Am79C971 I/O re- sources in all of I/O space located at offset 10h in the PCI Configuration Space. Bit Name Description ...
Page 112
... I/O base address. PCI Memory Mapped I/O Base Address Register Offset 14h The PCI Memory Mapped I/O Base Address register is a 32-bit register that determines the location of the Am79C971 I/O resources in all of memory space located at offset 14h in the PCI Configuration Space. Bit Name Description 31-5 MEMBASE Memory mapped I/O base ad- dress most significant 27 bits ...
Page 113
... Offset 2Ch The PCI Subsystem Vendor ID register is a 16-bit reg- ister that together with the PCI Subsystem ID uniquely identifies the add-in card or subsystem the Am79C971 controller is used in. Subsystem Vendor IDs can be ob- tained from the PCI SIG. A value of 0 (the default) indi- cates that the Am79C971 controller does not support subsystem identification ...
Page 114
... Offset 3Dh This PCI Interrupt Pin register is an 8-bit register that indicates the interrupt pin that the Am79C971 controller is using. The value for the Am79C971 Interrupt Pin reg- ister is 01h, which corresponds to INTA. The PCI Interrupt Pin register is located at offset 3Dh in the PCI Configuration Space ...
Page 115
... RDP access will de- pend upon the current setting of the RAP. RAP serves as a pointer into the CSR space. CSR0: Am79C971 Controller Status and Control Register Certain bits in CSR0 indicate the cause of an interrupt. The register is designed so that these indicator bits are cleared by writing ones to those bit locations ...
Page 116
... H_RESET, S_RESET set- ting the STOP bit. 11 MERR Memory Error is set by the Am79C971 controller when it re- quests the use of the system in- terface bus by asserting REQ and has not received GNT asser- tion after a programmable length of time. The length of time in mi- ...
Page 117
... Setting INIT clears the STOP bit. If STRT and INIT are set together, the Am79C971 controller initialization will be per- formed first. INIT is not cleared when the initialization sequence has completed. Read/Write accessible always. ...
Page 118
... BABLM Am79C971 dress registers and the buffer ad- dress registers which are stored on board the Am79C971 control- ler will be overwritten with the IADR[31:24] value, so that CSR accesses to these registers will show the 32-bit address that in- cludes the appended field. If SSIZE32 = 1, then software will ...
Page 119
... Am79C971 controller will scan through the next descriptor entries to locate the next STP bit that is set The Am79C971 controller will begin writing the next packets data to the buffer pointed to by that descriptor. Note that because several de- ...
Page 120
... If any of the entries that are examined during this Am79C971 controller ownership of the descriptor but also indicate STP = 0, then the Am79C971 controller will reset the OWN bit these entries scanned entry indicates host ownership with STP = 0, Am79C971 controller will not al- ter the entry, but will advance to the next entry ...
Page 121
... BSWP bit. Note that the byte ordering of the PCI bus is defined to be little En- dian. BSWP should not be set to 1 when the Am79C971 controller is used in a PCI bus application. Read/Write accessible always. BSWP is cleared by H_RESET or S_RESET and is not affected by STOP ...
Page 122
... H_RESET or S_RESET or by setting the STOP bit. Receive Collision Counter Over- flow is set by the Am79C971 con- troller when the Receive Collision Counter (CSR114 and CSR115) has wrapped around. When RCVCCO is set, INTA is asserted if IENA is 1 and the mask bit RCVCCOM is 0. ...
Page 123
... H_RESET or S_RESET and is unaffected by STOP. Reserved locations. Written as zeros and read as undefined. System Interrupt is set by the Am79C971 controller when it de- tects a system error during a bus master transfer on the PCI bus. System errors are data parity er- ror, master abort target abort. The setting of SINT due to ...
Page 124
... S_RESET or setting the STOP bit. Magic Packet Physical Logical Broadcast Accept. If MPPLBA is at its default value of 0, the Am79C971 controller will only de- tect a Magic Packet frame if the destination address of the packet matches the content of the physi- cal address register (PADR). If MPPLBA is set to 1, the destina- ...
Page 125
... Refer to the bit description of the FASTSPNDE bit and the Sus- pend section in Detailed Func- tions, Buffer Management Unit for details. In suspend mode, all of the CSR and BCR registers are accessi- ble. As long as the Am79C971 controller is not reset while CSR6: RX/TX Descriptor Table Length Bit ...
Page 126
... When a fast suspend is request- ed, the Am79C971 controller per- forms a quick entry into the suspend mode. At the time the SPND bit is set, the Am79C971 controller will complete the DMA process of any transmit and/or re- ceive packet that had already be- gun DMA activity. In addition, any ...
Page 127
... MREINTE 7 MAPINT is cleared by Am79C971 MII Management Read Error In- terrupt. The MII Read Error inter- rupt is set by the Am79C971 controller to indicate that the cur- rently read register from the ex- ternal PHY is invalid. The contents of BCR34 are incorrect and that the operation should be performed again ...
Page 128
... S_RESET or setting the STOP bit 5 MCCINT MII Management Complete Interrupt. The MII Man- agement Command Complete In- terrupt is set by the Am79C971 controller when a read or write operation to the MII Data Port (BCR34) is complete. When MCCINT is set to 1, INTA is asserted if the enable bit MC- CINTE is set to 1. ...
Page 129
... MIIPDTINT MII PHY Detect Transition Inter- rupt. The MII PHY Detect Transi- tion Interrupt is set by the Am79C971 controller whenever the MIIPD bit (BCR32, bit 14) transitions from vice ver- sa. Read/Write accessible always. MIIPDTINT is cleared by the host by writing a 1. Writing a 0 has no effect ...
Page 130
... STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR15: Mode This register’s fields are loaded during the Am79C971 controller initialization routine with the corresponding 130 Register, Initialization Block values, or when a direct register write has been performed on this register. ...
Page 131
... TSEL DAPC = 0, the 8-7 PORTSEL[1:0]Port Select bits allow for software 6 INTL Am79C971 (AUI mode) Transmit Mode Se- lect. TSEL controls the levels at which the AUI drivers rest when the AUI transmit port is idle. When TSEL = 0, DO+ and DO- yield “zero” differential to operate ...
Page 132
... DRTY Disable Retry. When DRTY is set to 1, the Am79C971 controller will attempt only one transmission. In this mode, the device will not pro- tect the first 64 bytes of frame data in the Transmit FIFO from being overwritten, because auto- matic retransmission will not be necessary ...
Page 133
... Description Reserved locations. Written as zeros and read as undefined. Contains the lower 16 bits of the current transmit buffer address from which the Am79C971 con- troller is transmitting. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP ...
Page 134
... CXBAU Contains the upper 16 bits of the current transmit buffer address from which the Am79C971 con- troller is transmitting. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR22: Next Receive Buffer Address Lower ...
Page 135
... Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR35: Current Transmit Descriptor Address Upper Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. Am79C971 135 ...
Page 136
... RES Reserved locations. Written as zeros and read as undefined. 15-0 CRST Current Receive Status. This field is a copy of bits 31-16 of RMD1 of the current receive de- scriptor. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. Am79C971 ...
Page 137
... Reserved locations. Written as zeros and read as undefined. 15-0 TXPOLLINT Transmit Polling Interval. This register contains the time that the Am79C971 controller will wait be- tween successive polling opera- tions. The TXPOLLINT value is expressed as the two’s comple- ment of the desired interval, where each bit of TXPOLLINT represents 1 clock period of time ...
Page 138
... H_RESET, S_RESET, or STOP. Description Reserved locations. Written as zeros and read as undefined. ister contains the time that the Am79C971 controller will wait be- tween successive polling opera- tions. The RXPOLLINT value is expressed as the two’s comple- ment of the desired interval, where each bit of RXPOLLINT ...
Page 139
... Note that since the advanced parity er- ror handling uses an additional bit in the descriptor, SWSTYLE (bits 7-0 of this register) must be set program the Am79C971 controller to use 32-bit software structures. APERREN does not affect the re- porting of address parity errors or ...
Page 140
... Description Reserved locations. Written as zeros and read as undefined. Contains the lower 16 bits of the previous transmit descriptor ad- dress pointer. Am79C971 con- troller has the capability to stack multiple transmit frames. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP ...
Page 141
... Reserved locations. Written as zeros and read as undefined. 15-0 NXBAL Contains the lower 16 bits of the next transmit buffer address from which the Am79C971 controller will transmit an outgoing frame. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP ...
Page 142
... Transmit Ring Length. Contains the two’s complement of the transmit descriptor ring length. This register is initialized during the Am79C971 controller initial- ization routine based on the value in the TLEN field of the initializa- tion block. However, this register can be manually altered. The ac- ...
Page 143
... RCVFW threshold is reached complete valid receive frame is detected (regardless of length). When the FDRPAD (BCR9, bit 2) is set and the Am79C971 control- ler is in full-duplex mode, in order to receive DMA to be performed for a new frame, at least 64 bytes must have been received. This effectively disables the runt pack- et accept feature in full duplex ...
Page 144
... Bus Transmit FIFO and the MAC Transmit FIFO. The Am79C971 controller supports a mode that will wait un- til a full packet is available before commencing with the transmis- sion of preamble. This mode is useful in a system where high la- tencies cannot be avoided ...
Page 145
... PARTID Am79C971 issuing increment commands to increment the memory address for sequential operations. The DMABAU register is undefined until the first Am79C971 control- ler DMA operation. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP ...
Page 146
... STOP or the SPND bit is set. VER is read only. VER is read only. Write operations are ig- nored. 11-0 PARTIDU Upper 12 bits of the Am79C971 controller part number, i.e., 0010 0110 0010b (262h). Read accessible only when either the STOP or the SPND bit is set. VER is read only. PARTIDU is read only ...
Page 147
... RCVALGN H_RESET or is cleared by CSR124: Test Register 1 This register is used to place the Am79C971 controller into various test modes. The Runt Packet Accept is the only user accessible test mode. All other test modes are for AMD internal use only. Bit Name 31-16 RES ...
Page 148
... Bus Configuration Registers The Bus Configuration Registers (BCR) are used to program the configuration of the bus interface and other special features of the Am79C971 controller that are not related to the IEEE 8802-3 MAC functions. The BCRs are accessed by first setting the appropriate bit ...
Page 149
... Reserved locations. Written as zeros and read as undefined Writing to these registers have no effect on the opera- tion of the Am79C971 controller. Writes to those registers marked as “Reserved” will have no effect. Reads from these locations will produce undefined values. Table 30. BCR Registers ...
Page 150
... INTA pin is configured for edge- sensitive applications. In this mode, an interrupt request is sig- naled by a high level driven on the INTA pin by the Am79C971 controller. When the interrupt is cleared, the INTA pin is driven to a low level by the Am79C971 controller. This mode is intended for systems that do not allow ...
Page 151
... INTLEVEL should not be set to 1 when the Am79C971 controller is used in a PCI bus application. Read/Write accessible always. INTLEVEL is cleared H_RESET and is unaffected by S_RESET or by setting the STOP bit. 6-4 RES Reserved locations. Written as zeros and read as undefined. ...
Page 152
... Table 31. Network Port Configuration Link Status (of 10BASE-T) Fail Pass Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care 13 LEDDIS Am79C971 MII Status Network (BCR32[14]) Port 0 AUI 0 10BASE-T 1 MII Don’t Care AUI Don’ ...
Page 153
... S_RESET or setting the STOP bit. Full-Duplex Link Status Enable. Indicates the Full-Duplex Link Test Status. When this bit is set, a value passed to the LED- OUT signal when the Am79C971 controller is functioning in a Link Pass state and full-duplex opera- tion is enabled. ...
Page 154
... S_RESET or setting the STOP bit. Jabber Status Enable. When this bit is set, a value passed to the LEDOUT bit in this register when the Am79C971 controller is jabbering on the network. Read/Write accessible always. JABE is cleared by H_RESET and is not affected by S_RESET or setting the STOP bit. ...
Page 155
... STOP bit. 100 Mbps Enable. When this bit is set value passed to the LEDOUT bit in this register when the Am79C971 controller is operating at 100 Mbps mode. The indication is valid with both the in- ternal and external PHYs. Read/Write accessible always. ...
Page 156
... LED- OUT signal when the Am79C971 controller is functioning in a Link Pass state and full-duplex opera- tion is enabled. Am79C971 controller is not func- tioning in a Link Pass state with 156 PSE When the ...
Page 157
... STOP bit. 1 JABE Jabber Status Enable. When this bit is set, a value passed to the LEDOUT bit in this register when the Am79C971 controller is jabbering on the network COLE BCR6: LED2 Status BCR6 controls the function(s) that the LED2 pin dis- plays ...
Page 158
... Mbps Enable. When this bit is set value passed to the LEDOUT bit in this register when the Am79C971 controller is operating at 100 Mbps mode. The indication is valid with both the in- ternal and external PHYs. 158 ...
Page 159
... STOP bit. 8 FDLSE Full-Duplex Link Status Enable. Indicates the Full-Duplex Link Test Status. When this bit is set, a value passed to the LED- OUT signal when the Am79C971 controller is functioning in a Link Pass state and full-duplex opera- tion is enabled. Am79C971 controller is not func- ...
Page 160
... STOP bit. 1 JABE Jabber Status Enable. When this bit is set, a value passed to the LEDOUT bit in this register when the Am79C971 controller is jabbering on the network. Read/Write accessible always. JABE is cleared by H_RESET and is not affected by S_RESET or setting the STOP bit. ...
Page 161
... S_RESET or setting the STOP bit. Full-Duplex Link Status Enable. Indicates the Full-Duplex Link Test Status. When this bit is set, a value passed to the LED- OUT signal when the Am79C971 controller is functioning in a Link Pass state and full-duplex opera- tion is enabled. ...
Page 162
... S_RESET or setting the STOP bit. Jabber Status Enable. When this bit is set, a value passed to the LEDOUT bit in this register when the Am79C971 controller is jabbering on the network. Read/Write accessible always. JABE is cleared by H_RESET and is not affected by S_RESET or setting the STOP bit. ...
Page 163
... When FDEN is cleared, full-duplex operation is not enabled and the Am79C971 controller will always operate in the half-duplex mode. When FDEN is set, the Am79C971 con- troller will operate in full-duplex mode when the 10BASE-T or MII port is enabled or when the AUI port is enabled and the AUIFD (BCR9, bit 1) bit is set ...
Page 164
... Am79C971 controller latches in the data on the bits of the Expansion Bus Data inputs. ROMTMG, during write operations, defines the time from when the Am79C971 controller drives the lower bits of the Expansion Bus Data to when the 164 Table 32 ...
Page 165
... MEMCMD 8 EXTREQ controller before Am79C971 The NOUFLO bit should not be set when the Am79C971 control- ler is operating in the NO-SRAM mode with no external SRAM. Read/Write accessible only when either the STOP or the SPND bit is set. NOUFLO is cleared to 0 af- ter H_RESET or S_RESET and is unaffected by STOP ...
Page 166
... Reserved locations. Read acces- sible always; write accessible only when either the STOP or the SPND bit is set. After H_RESET, the value in these bits will be 001b. The setting of these bits have no effect on any Am79C971 controller function. LINBC is not affected by S_RESET or STOP. ...
Page 167
... EEPROM locations may be accessed directly through BCR19. At the end of the read operation, the PREAD bit will automatically be reset the Am79C971 controller and PVALID will bet set, provided that an EEPROM existed on the interface pins and that the checksum for the entire 64 bytes of EEPROM was cor- rect ...
Page 168
... EEPROM programmable lo- cations will be equal to the H_RESET programming those locations PREAD command is given to the Am79C971 controller and the auto-detection pin (EESK/LED1/ SFBD) indicates that no EE- PROM is present, then the EE- PROM read operation will still be attempted. Note that at the end of the ...
Page 169
... PVALID is reset to 0. EEPROM read operation is attempted. Entire read sequence will occur, checksum operation will pass, PVALID is set to 1. Am79C971 hold times of the EEDI pin value with respect to the EESK signal edge are not guaranteed. ESK has no effect on the EESK pin unless the PREAD bit is set to 0 and the EEN bit is set to 1 ...
Page 170
... Note that since the advanced parity er- ror handling uses an additional bit in the descriptor, SWSTYLE (bits 7-0 of this register) must be set program the Am79C971 controller to use 32-bit software structures. APERREN does not affect the re- porting of address parity errors or ...
Page 171
... MAX_LAT is aliased to the PCI configuration space register MAX_LAT (offset 3Fh). The host will use the value in the register to determine the setting of the Am79C971 Latency Timer register. Read accessible always; write accessible only when either the STOP or the SPND bit is set. ...
Page 172
... MIN_GNT is set to the value of 06h by H_RESET which results in a default minimum grant of 1.5 s, which is the time it takes the Am79C971 controller to read/ write half of the FIFO. (16 DWord transfers in burst mode with one extra wait state per data phase inserted by the target.) Note that the default is only a typical value ...
Page 173
... Note: The minimum allowed number of pages is eight for nor- mal network Am79C971 controller will not op- erate correctly with less than the eight pages of memory. When the minimum number of pages is used, these pages must be allo- cated four each for transmit and receive. Also note that a “ ...
Page 174
... SRAM_SIZE (BCR25, bits 7-0) bits are non-zero. SRAM_BND (BCR26, bits 7-0) has no mean- ing when the Am79C971 control- ler is in the Low Latency mode. See the section on SRAM Config- uration for more details. When the LOLATRX bit is set to ...
Page 175
... BCR29: Expansion Port Address Upper (Used for Flash/EPROM Accesses) Bit Name 31-16 RES 15 FLASH 14 LAAINC Am79C971 SRAM accesses are word orient- ed only, EPADDRL[0] is the least significant word address bit. On any byte write accesses to the SRAM, the user will have to fol- low the read-modify-write scheme ...
Page 176
... BCR31: Software Timer Register Bit Name 31-16 RES 15-0 STVAL Am79C971 port. The Flash and SRAM ac- cesses use different address phases. Incorrect configuration will result in a possible corruption of data. Flash read cycles are performed when BCR30 is read and the FLASH bit (BCR29, bit 15) is set to 1 ...
Page 177
... PHY. APEP when set to 1 the Am79C971 controller will poll the MII status register in the external PHY. This feature allows the soft- ware driver or upper layers to see any changes in the status of the external PHY. An interrupt when enabled is generated when the contents of the new status is dif- ferent from the previous status ...
Page 178
... Read/write accessible always. DANAS is set H_RESET and is unaffected by S_RESET and the STOP bit. 6 XPHYRST External PHY Reset. When XPH- YRST is set, the Am79C971 con- troller after an H_RESET or S_RESET will issue an MII man- 178 during ...
Page 179
... Am79C971 con- troller to work seamlessly with the Micro Linear 6692 PHY. See the section on Working with Micro Linear 6692 for details. Read/Write accessible always. MII L is set H_RESET and is unaffected by S_RESET and the STOP bit. valid when the internal Network Port Manager is scanning for a network port ...
Page 180
... DWord boundary, i.e., CSR1, bit 1 and 0 must be cleared to 0. When SSIZE32 is set to 0, the initialization block looks like Table 42. Note: The Am79C971 controller performs DWord ac- cesses to read the initialization block. This statement is always true, regardless of the setting of the SSIZE32 bit. ...
Page 181
... Each DRE must be located at an 8-byte address boundary when SSIZE32 is set to 0 (BCR20, bit 8). Table 44. R/TLEN Decoding (SSIZE32 = 0) R/TLEN 000 001 010 011 100 101 110 111 Am79C971 Bits 7-4 Bits 3-0 RDRA 23-16 TDRA 23-16 Bits Bits Bits 11-8 7-4 3-0 MODE PADR 47-32 ...
Page 182
... SEL 64 6 Figure 57. Address Match Logic (IEEE/ANSI 802.3) maps to the Am79C971 PADR reg- ister as follows: the first byte is compared with PADR[7:0], with PADR[0] being the least significant bit of the byte. The second ISO 8802-3 (IEEE/ANSI 802.3) byte is compared with PADR[15:8], again from the least significant bit to the most significant bit, and so on ...
Page 183
... Description This bit indicates whether the de- scriptor entry is owned by the host (OWN = the Am79C971 controller (OWN = 1). The Am79C971 controller clears the OWN bit after filling the buffer that the descriptor points to. The host sets the OWN bit after emp- ...
Page 184
... FIFO into a memory buffer before the internal FIFO overflowed. OFLO is set by the Am79C971 controller and cleared by the host. 27 CRC CRC indicates that the receiver has detected a CRC (FCS) error on the incoming frame ...
Page 185
... PAM is valid only when ENP is set. PAM is set by the Am79C971 controller and cleared by the host. This bit does not exist when the Am79C971 controller is pro- grammed to use 16-bit software ...
Page 186
... RES USER SPACE LCOL LCAR RTRY MORE/ ONE DEF STP ENP LTINT TBADR[31:0] USER SPACE Am79C971 Description Transmit Buffer address. This field contains the address of the transmit buffer that is associated with this descriptor 7-0 STP ENP TBADR[23:16] BCNT TDR 23 22-16 15-12 11-4 ...
Page 187
... LTINT is used to suppress inter- rupts after successful transmis- sion on selected frames. When LTINT is cleared to 0 and ENP is set to 1, the Am79C971 controller will not set TINT (CSR0, bit 9) af- ter a successful transmission. TINT will only be set when the last descriptor of a frame has both LTINT and ENP set to 1 ...
Page 188
... Am79C971 controller will only set BPE when the advanced parity error handling is enabled by set- ting APERREN (BCR20, bit 10 BPE is set by the Am79C971 controller and cleared by the host. This bit does not exist, when the Am79C971 controller is pro- grammed to use 16-bit software ...
Page 189
... RETRY error occurs, the count will roll over this case only, the Transmit Retry Count value of 0 should be interpreted as meaning 16. TRC is written by the Am79C971 con- troller into the last transmit de- scriptor of a frame, or when an error terminates a frame. Valid only when OWN is cleared to 0. ...
Page 190
... Am79C971 Default Value 1022h 2000h 0000h 0280h 10h 00h 00h 02h 00h 00h 00h 00h 0000 0001h 0000 0000h 00h 00h 00h 0000 0000h 00h 00h 01h 06h FFh ...
Page 191
... CSR33 uuuu uuuu Note undefined value Running register Setup register Test register; all default values are in hexadecimal format. Comments Am79C971 Controller Status Register Lower IADR: maps to location 16 Upper IADR: maps to location 17 Interrupt Masks and Deferral Control Test and Features Control Extended Control and Interrupt 1 ...
Page 192
... PXDAU: Previous XMT Descriptor Address Upper PXBC: Previous Transmit Byte Count PXST: Previous Transmit Status NXBAL: Next XMT Buffer Address Lower NXBAU: Next XMT Buffer Address Upper NXBC: Next Transmit Byte Count NXST: Next Transmit Status Reserved Reserved Reserved Am79C971 Use ...
Page 193
... DMABC: Buffer Byte Counter Reserved Chip ID Register Lower Chip ID Register Upper Reserved Reserved RCON: Ring Length Conversion Reserved Reserved Reserved Reserved Reserved Reserved Reserved Bus Timeout Reserved Reserved Reserved Reserved Reserved Reserved Reserved Am79C971 Use 193 ...
Page 194
... CSR127 uuuu uuuu 194 Reserved Reserved Reserved Reserved Missed Frame Count Reserved Received Collision Count Reserved Reserved Reserved Reserved Reserved Reserved Reserved Receive Frame Alignment Control Reserved Test Register 1 MAC Enhanced Configuration Control Reserved Reserved Am79C971 Use ...
Page 195
... Expansion Bus Address Lower N/A Expansion Bus Address Upper N/A Expansion Bus Data Port FFFFh Software Timer Value 0000h MII Control and Status N/A MII Address N/A MII Management Data 1022h PCI Vendor ID Am79C971 Programmability User EEPROM Yes Yes No No Yes Yes Yes ...
Page 196
... REGISTER PROGRAMMING SUMMARY Am79C971 Programmable Registers Am79C971 Control and Status Registers Register CSR0 Status and control bits: (DEFAULT = 0004) 8000 ERR 4000 BABL 2000 CERR 1000 MISS CSR1 Lower IADR (Maps to CSR 16) CSR2 Upper IADR (Maps to CSR 17) CSR3 Interrupt masks and Deferral Control: (DEFAULT = 0) ...
Page 197
... AM79C971 CONTROL AND STATUS REGISTERS (CONTINUED) Register CSR58 Software Style (mapped to BCR20) bits [7:0] = SWSTYLE, Software Style Register. 0000 0002 8000 -- 4000 -- 2000 -- 1000 -- CSR76 RCVRL: RCV Descriptor Ring length CSR78 XMTRL: XMT Descriptor Ring length CSR80 FIFO threshold and DMA burst control. (DEFAULT = 2810) ...
Page 198
... Am79C971 Bus Configuration Registers RAP Addr Register 0 MSRDA Programs width of DMA read signal (DEFAULT = 5) 1 MSWRA Programs width of DMA write signal (DEFAULT = Miscellaneous Configuration bits: (DEFAULT = 2) 8000 -- 4000 TMAULOOP 2000 -- 1000 -- 4 LED0 Programs the function and width of the LED0 signal. (DEFAULT = 00C0) ...
Page 199
... AM79C971 BUS CONFIGURATION REGISTERS (CONTINUED) 20 SWSTYLE Software Style (DEFAULT = 0000, maps to CSR 58) 21 INTCON Interrupt Control 8000 4000 2000 1000 22 PCILAT PCI Latency (DEFAULT = FF06) bits [15:8] = MAX_LAT bits [7:0] = MIN_GNT 25 SRAMSIZE SRAM Size (DEFAULT = 000) bits [7:0] = SRAM_SIZE 26 SRAMBND SRAM Boundary (DEFAULT = 0000) ...
Page 200
... OL1 OL2 OL3 (Note (Note 3) VIN = DDB 0.4V OUT IOL = 1.5 mA IOH = -0.5 mA Am79C971 ..........+ DD_PLL DD for 3.3-V Signaling) ..............+ 3 DD_PCI - 0 0.5V, IN DD_PLL 0 < ...