CY7C68013 Cypress Semiconductor Corporation., CY7C68013 Datasheet

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... RAM USB Engine “Soft Configuration” FIFO and endpoint memory Easy firmware changes (master or slave operation) Figure 1-1. Block Diagram • 3901 North First Street • CY7C68013 C-compatible controller, runs at 100 or 400 Compatible Master Abundant I/O including two USARTS General ADDR (9) programmable I/F ...

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... The four I/O ports A–D use the SFR addresses used in the standard 8051 for ports 0–3, which are not imple- mented in FX2. Because of the faster and more efficient SFR addressing, the FX2 I/O ports are not addressable in external RAM space (using the MOVX instruction). CY7C68013 Page ...

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... To do this, the FX2 must enumerate in the full speed mode and then, when configured, renumerate in high speed mode. For an example of the benefits and limitations of this renumeration process see the application note titled “Bus Powered Enumeration with FX2”. CY7C68013 SCON1 ...

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... EP8 OUT was Pinged and it NAK’d Bus errors exceeded the programmed limit reserved reserved reserved ISO EP2 OUT PID sequence error ISO EP4 OUT PID sequence error ISO EP6 OUT PID sequence error ISO EP8 OUT PID sequence error CY7C68013 Notes Page ...

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... USB download • USB upload • Setup data pointer 2 • I C-compatible interface boot load. 3.10.3 External Code Memory The bottom eight kbytes of program memory is external, and therefore the bottom eight kbytes of internal RAM is accessible only as data memory. CY7C68013 Notes Page ...

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... External 64 kbytes Data External Memory Code (RD#,WR#) Memory (PSEN#) (Ok to populate Eight kbytes data memory RAM here—RD#/WR# Data strobes are not (RD#,WR#)* active) Data Code 2 C-compatible interface boot access Figure 3-2. External Code Memory CY7C68013 Code Page ...

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... EP6&8, since none of the 512-byte buffers are combined between these endpoint groups. An example endpoint config- uration would be: EP2—1024 double buffered; EP6—512 quad buffered. To the right of the vertical line, buffers are shared between EP2–8, and therefore only entire columns may be chosen. CY7C68013 Page ...

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... CY7C68013 1024 1024 1024 1024 EP2 EP2 1024 ...

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... GPIF The GPIF is a flexible 8- or 16-bit parallel interface driven by a user-programmable finite state machine. It allows the CY7C68013 to perform local bus mastering, and can implement a wide variety of protocols such as ATA interface, printer parallel port, and Utopia. The GPIF has six programmable control outputs (CTL), nine address outputs (GPIFADRx), and six general-purpose ready inputs (RDY) ...

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... Note that two of the required signals, RD# and WR#, are present in the 100-pin version. In the 100-pin and 128-pin versions, an 8051 control bit can be set to pulse the RD# and WR# pins when the 8051 reads from/writes to PORTC. CY7C68013 2 C-compatible interface boot loader will and 512 ...

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... RxD1 TxD1 INT4 INT5# TIMER2 TIMER1 TIMER0 RD# WR# CS# OE# PSEN# A15 A14 A13 A12 A11 A10 128 Figure 4-1. Signals CY7C68013 Slave FIFO FD[15] FD[14] FD[13] FD[12] FD[11] FD[10] FD[9] FD[8] FD[7] FD[6] FD[5] FD[4] FD[3] FD[2] FD[1] FD[0] SLRD SLWR FLAGA FLAGB FLAGC INT0#/ PA0 INT1#/ PA1 SLOE WU2/PA3 FIFOADR0 FIFOADR1 PKTEND ...

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... GND 27 INT4 IFCLK 32 RESERVED 33 34 BKPT EA 35 SCL 36 SDA 37 OE# 38 Figure 4-2. CY7C68013 128-pin TQFP Pin Assignment Document #: 38-08012 Rev. *E CY7C68013 128-pin TQFP * denotes programmable polarity CY7C68013 102 PD0/FD8 101 *WAKEUP 100 VCC 99 RESET# 98 CTL5 ...

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... GND 19 VCC 20 GND 21 INT4 IFCLK 26 RESERVED 27 BKPT 28 SCL 29 SDA 30 Figure 4-3. CY7C68013 100-pin TQFP Pin Assignment Document #: 38-08012 Rev. *E PA7/*FLAGD/SLCS# CY7C68013 100-pin TQFP * denotes programmable polarity CY7C68013 PD0/FD8 80 *WAKEUP 79 VCC 78 RESET# 77 CTL5 76 GND 75 74 PA6/*PKTEND 73 PA5/FIFOADR1 72 PA4/FIFOADR0 ...

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... Figure 4-4. CY7C68013 56-pin SSOP Pin Assignment Document #: 38-08012 Rev. *E CY7C68013 56-pin SSOP PD5/FD13 PD4/FD12 PD6/FD14 PD3/FD11 PD7/FD15 PD2/FD10 GND PD1/FD9 CLKOUT PD0/FD8 VCC *WAKEUP GND VCC RDY0/*SLRD RESET# RDY1/*SLWR ...

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... XTALOUT 4 XTALIN 5 AGND 6 VCC 7 DPLUS 8 DMINUS 9 GND 10 VCC 11 GND 12 *IFCLK 13 14 RESERVED Figure 4-5. CY7C68013 56-pin QFN Pin Assignment Document #: 38-08012 Rev. *E CY7C68013 56-pin QFN * denotes programmable polarity CY7C68013 RESET# 42 GND 41 PA7/*FLAGD/SLCS# 40 PA6/*PKTEND 39 PA5/FIFOADR1 38 PA4/FIFOADR0 37 PA3/*WU2 36 PA2/*SLOE 35 PA1/INT1# ...

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... CY7C68013 Pin Descriptions [5] Table 4-1. FX2 Pin Descriptions 128 100 56 56 TQFP TQFP SSOP QFN Name AVCC AGND DMINUS DPLUS 117 A4 118 A5 119 A6 120 A7 126 A8 127 A9 128 A10 21 A11 22 A12 ...

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... FIFOADR1 is an input-only address select for the slave FIFOs connected to FD[7..0] or FD[15..0]. I/O/Z I Multiplexed pin whose function is selected by the IFCONFIG[1:0] (PA6) bits. PA6 is a bidirectional I/O port pin. PKTEND is an input-only packet end with programmable polarity (FIFOPOLAR.5) for the slave FIFOs connected to FD[7..0] or FD[15..0]. CY7C68013 Description Page ...

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... GPIFADR2 is a GPIF address output pin. I/O/Z I Multiplexed pin whose function is selected by PORTCCFG.3 (PC3) PC3 is a bidirectional I/O port pin. GPIFADR3 is a GPIF address output pin. I/O/Z I Multiplexed pin whose function is selected by PORTCCFG.4 (PC4) PC4 is a bidirectional I/O port pin. GPIFADR4 is a GPIF address output pin. CY7C68013 Description Page ...

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... PE1 is a bidirectional I/O port pin. T1OUT is an active-HIGH signal from 8051 Timer-counter1. T1OUT outputs a high level for one CLKOUT clock cycle when Timer1 overflows. If Timer1 is operated in Mode 3 (two separate timer/counters), T1OUT is active when the low byte timer/counter overflows. CY7C68013 Description Page ...

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... SLWR is the input-only write strobe with programmable polarity (FIFOPOLAR.2) for the slave FIFOs connected to FDI[7..0] or FDI[15..0]. Input N/A RDY2 is a GPIF input signal. Input N/A RDY3 is a GPIF input signal. Input N/A RDY4 is a GPIF input signal. Input N/A RDY5 is a GPIF input signal. CY7C68013 Description Page ...

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... TXD0 is the active-HIGH TXD0 output from 8051 UART0, which provides the output clock in sync mode, and the output data in async mode. Output H CS# is the active-LOW chip select for external memory. Output H WR# is the active-LOW write strobe output for external memory. CY7C68013 Description Page ...

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... Ground. Ground N/A Ground. Ground N/A Ground. Ground N/A Ground. Ground N/A Ground. Ground N/A Ground. N/A N/A No-connect. This pin must be left open. N/A N/A No-connect. This pin must be left open. N/A N/A No-connect. This pin must be left open. CY7C68013 Description  with C-compatible peripheral is attached. with a 2.2K CC Page ...

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... PL7 PL6 PL5 PL4 PL3 DECIS PKTSTAT IN:PKTS[2] IN:PKTS[1] IN:PKTS[0] OUT:PFC12 OUT:PFC11 OUT:PFC10 DECIS PKTSTAT OUT:PFC12 OUT:PFC11 OUT:PFC10 PFC7 PFC6 PFC5 PFC4 PFC3 CY7C68013 Default Access xxxxxxxx RW CLKINV CLKOE 8051RES 00000010 rrbbbbbr GSTATE IFCFG1 IFCFG0 11000000 RW FLAGA2 FLAGA1 FLAGA0 ...

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... EC3 EC2 EC1 EC0 LIMIT3 I2V4 I2V3 I2V2 I2V1 1 0 I4V3 I4V2 I4V1 AV2EN CY7C68013 Default PFC2 PFC1 PFC0 00000000 0 0 PFC8 10001000 bbrbbrrb 0 0 PFC8 10001000 bbrbbrrb PFC2 PFC1 PFC0 00000000 PFC2 PFC1 PFC0 00000000 ...

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... FULL 0 0 NPAK1 NPAK0 FULL BC12 BC11 CY7C68013 Default Access 0 INT1 INT0 00000000 RW GPIFA2 GPIFA1 GPIFA0 00000000 RW T2OUT T1OUT T0OUT 00000000 RW BERR ACK DONE 000xx000 bbbrrrrr xxxxxxxx RW 0 STOPIE ...

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... TC6 TC5 TC4 TC3 CY7C68013 Default BC2 BC1 BC0 00000000 0 BC10 BC9 BC8 00000000 BC2 BC1 BC0 00000000 BC10 BC9 BC8 00000000 BC2 BC1 BC0 00000000 0 BC10 ...

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... T2M T1M T0M IE5 IE4 I²CINT USBNT 1 A15 A14 A13 A12 A11 SM0_0 SM1_0 SM2_0 REN_0 TB8_0 CY7C68013 Default Access 0 FS1 FS0 00000000 FIFO6FLAG 00000000 xxxxxxxx W 0 FS1 FS0 00000000 FIFO8FLAG 00000000 ...

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... D12 D11 RS1 RS0 SMOD1 1 ERESI RESI INT6 EX6 EX5 PX6 PX5 CY7C68013 Default Access A10 A9 A8 00000000 00000000 RW A10 A9 A8 00000000 00000000 xxxxxxxx ...

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... Crystal Frequency) ... 24 MHz ± 100 ppm OSC + 0.5V CC Conditions 0< V < OUT I = –4 mA OUT Except D+/D– D+/D– Connected Disconnected 8051 running, connected to USB HS 8051 running, connected to USB FS V min. = 3.0V CC CY7C68013 Parallel Resonant Min. Typ. Max. Unit 3.0 3.3 3 5.25 V –0.5 0.8 V µA ±10 2 ...

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... CL AV DSU t (48 MHz) = 3*t – t – ns. ACC1 CL AV DSU Document #: 38-08012 Rev STBH [11 ACC1 data in Min. Typ. 20.83 41.66 83 9.6 0 CY7C68013 Max. Unit Notes ns 48 MHz ns 24 MHz ns 12 MHz 10 11 Page ...

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... DSU Document #: 38-08012 Rev. *E Stretch = STBH STBL t SCSL t SOEL t DSU [12 ACC1 data in Stretch = 1 [12] t ACC1 Min. Typ. 20.83 41.66 83.2 9.6 0 CY7C68013 t DSU t DH data in Max. Unit Notes ns 48 MHz ns 24 MHz ns 12 MHz 10 11 Page ...

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... Clock to WR Pulse HIGH STBH t Clock to CS Pulse LOW SCSL t Clock to Data Turn-on ON1 t Clock to Data Hold Time OFF1 Document #: 38-08012 Rev STBH AV t OFF1 data out Stretch = 1 data out Min. Max. 0 10.7 0 11.2 0 11.2 13.0 0 13.1 0 13.1 CY7C68013 t OFF1 Unit Notes Page ...

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... IFCLK must not exceed 48 MHz. Document #: 38-08012 Rev IFCLK t SGA t SRY t RYH valid t t SGD DAH t XCTL N N+1 t XGD Description Min. 20.83 8.9 9.2 Description Min. 20.83 2.9 3.7 3.2 4.5 CY7C68013 [13] [14, 15] Max. Unit 7 6.7 ns [15] Max. Unit 200 11 10.7 ns ...

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... Clock to FLAGS Output Propagation Delay XFLG t Clock to FIFO Data Output Propagation Delay XFD Document #: 38-08012 Rev IFCLK t RDH t SRD t XFLG N N OEon XFD Description Min. 20.83 18.7 Description Min. 20.83 12.7 3.7 CY7C68013 t OEoff [13] [15] Max. Unit 10.5 ns 10 [15] Max. Unit 200 10 ...

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... Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz. Document #: 38-08012 Rev RDpwh t RDpwl t XFLG t XFD N N OEon OEoff [16] Description Min. t IFCLK t WRH t SWR SFD FDH t XFLG Description Min. 20.83 18.1 9.2 CY7C68013 [13] Max. Unit 10 [13] [15] Max. Unit 9.5 ns Page ...

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... Clock to FLAGS Output Propagation Delay XFLG Document #: 38-08012 Rev. *E Description Min. 20.83 12.1 3.6 3.2 4.5 t WRpwh t WRpwl t t FDH SFD t XFD Description Min. t PEH t SPE t XFLG Description Min. 20.83 14.6 CY7C68013 [15] Max. Unit 200 13.5 ns [13] [16] Max. Unit [13] [15] Max. Unit ns ns ...

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... Failing to adhere to this timing, will result in the FX2 failing to send the one byte/word short packet FDH SFD FDH FDH SFD SFD X-2 X-1 X-3 CY7C68013 [15] Max. Unit 200 13 FAH >= t WRH SFD ...

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... FIFOADR[1:0] to FLAGS Output Propagation Delay XFLG t FIFOADR[1:0] to FIFODATA Output Propagation Delay XFD Document #: 38-08012 Rev PEpwh t PEpwl t XFLG [16] Description Min. t OEoff t OEon Description Min. t XFLG t XFD N N+1 Description Min. CY7C68013 [13] Max. Unit 115 ns [13] Max. Unit 10.5 ns 10.5 ns [13] Max. Unit 10.7 ns 14.3 ns Page ...

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... FIFOADR[1:0] to RD/WR/PKTEND Set-up Time SFA t SLRD/PKTEND to FIFOADR[1:0] Hold Time FAH t SLWR/PKTEND to FIFOADR[1:0] Hold Time FAH Document #: 38-08012 Rev SFA FAH [15] Description Min. 20.83 t FAH t SFA [16] Description Min. CY7C68013 Max. Unit 200 [13] Max. Unit Page ...

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... During the first read cycle, on the rising edge of the clock the FIFO pointer is updated and increments to point to address N+1. For each subsequent rising edge of IFCLK, while the SLRD is asserted, the FIFO pointer is incre- mented and the next data value is placed on the data bus. CY7C68013 t FAH >= t RDH ...

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... PKTEND pin at least one clock cycle after the rising edge that caused the last byte/word to be clocked into the previous auto committed packet (the packet with the number of bytes equal to what is set in the AUTOINLEN register). Refer to Figure 9- 10 for further details on this timing. CY7C68013 t FAH >= t WRH ...

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... through 5. Note: In burst read mode, during SLOE is assertion, the data bus driven state and outputs the previous data. Once SLRD is asserted, the data from the FIFO is driven on the data bus (SLOE must also be asserted) and then the FIFO pointer is incremented. CY7C68013 t FAH t t ...

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... SLWR and the PKTEND signal at the same time. It should be designed to assert the PKTEND after SLWR is deasserted and met the minimum de- before the SFD asserted pulse width. The FIFOADDR lines are to be held constant during the PKTEND assertion. from the XFLG CY7C68013 t FAH t WRpwh T=9 t XFLG t ...

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... TQFP CY7C68013-100AC 100 TQFP CY7C68013-56PVC 56 SSOP CY7C68013-56LFC 56 QFN CY7C68013-128AXC 128 TQFP Lead-Free Package CY7C68013-100AXC 100 TQFP Lead-Free Package CY7C68013-56PVXC 56 SSOP Lead-Free Package CY7C68013-56LFXC 56 QFN Lead-Free Package CY3681 EZ-USB FX2 Xcelerator Development Kit Document #: 38-08012 Rev. *E RAM Size # Prog I/Os 8051 Address/Data Buses 8K ...

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... SIDE VIEW 0.08[0.003] C 1.00[0.039] MAX. 0.05[0.002] MAX. 0.80[0.031] MAX. 0.20[0.008] REF. 0.30[0.012] 0.50[0.020] 0°-12° C SEATING PLANE Figure 11-2. 56-Lead QFN LF56A CY7C68013 51-85062-*C BOTTOM VIEW 0.18[0.007] 0.28[0.011] PIN1 ID N 0.20[0.008 0.45[0.018] E-PAD (PAD SIZE VARY BY DEVICE TYPE) 0.24[0.009] (4X) 0 ...

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... Figure 11-3. 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 Figure 11-4. 128-Lead Thin Plastic Quad Flatpack ( 1.4 mm) A128 Document #: 38-08012 Rev. *E CY7C68013 51-85050-*A 51-85101-*B Page ...

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... PCB Material This figure only shows the top three layers of the circuit board: Top Solder, PCB Dielectric, and the Ground Plane Figure 13-3. X-ray Image of the Assembly 2 C system, provided that the system conforms to the I CY7C68013 2 C Standard Specification Page ...

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... Document History Page Document Title: CY7C68013 EZ-USB FX2™ USB Microcontroller High-speed USB Peripheral Controller Document Number: 38-08012 Orig. of REV. ECN NO. Issue Date Change ** 111753 11/15/01 DSG *A 111802 02/20/02 KKU *B 115480 06/26/02 KKU *C 120776 01/06/03 KKU *D 288810 See ECN MON *E 317674 See ECN MON Document #: 38-08012 Rev. *E ...