CDP1855CE Intersil Corporation, CDP1855CE Datasheet
CDP1855CE
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CDP1855CE Summary of contents
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... Direct Interface to CDP1800-Series Microprocessors • Easy Interface to Other 8-Bit Microprocessors • Significantly Increases Throughput of Microprocessor Used for Arithmetic Calculations Ordering Information PACKAGE TEMP. RANGE PDIP - +85 C CDP1855CE Burn-In CDP1855CEX o o SBDIP - +85 C CDP1855CD CDP1855D D28.6 Burn-In CDP1855CDX Pinout ...
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Absolute Maximum Ratings DC Supply Voltage Range (All voltage values referenced to V terminal) SS CDP1855 . . . . . . . . . . . . . . . . . . . . . ...
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Recommended Operating Conditions should be selected so that operation is always within the following ranges: PARAMETER DC Operating Voltage Range Input Voltage Range Maximum Clock Input Frequency Minimum Multiply (16 8 Divide) Time CE RA2 RA1 RA0 ...
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Functional Description The CDP1855 is a multiply-divide unit (MDU) designed to be compatible with CDP1800 series microprocessor systems. It can, in fact, be interfaced to most 8-bit microprocessors (see Figure 5). The CDP1855 performs binary multiply or divide operations as ...
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A second division is performed using the remainder from the first division ( the more significant 8N-bits of the divi- dend and the less significant half of the original dividend loaded into the Z register. The divisor in ...
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RD/WE - Read/Write Enable (Input): This signal defines whether the selected register read from or written to. In 1800 systems use MRD if MDU's are addressed as I/O devices, MWR is used if MDU's are addressed as ...
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BUS 7 BUS 6 BUS RESET SEQUENCE COUNTER SELECT SHIFT RATE OPTIONS SHIFT = CLOCK FREQUENCY RATE BIT OUTPUT NOTES ...
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CDP1855 Interfacing Schemes CLEAR XTAL MA0 MA1 HIGH ADDRESS MAX LATCH CDP1802 TPA MWR MRD TPB EF BUS FIGURE 3. REQUIRED CONNECTION FOR MEMORY MAPPED ADDRESSING OF THE MDU Programming Example for Multiplication For a 24-bit x 24-bit multiply using ...
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Programming Example for Multiplication For a 24-bit x 24-bit multiply using the system shown in Figure 5, the following is an assembly listing of a program to multiply 201F7C 723C09 : (Continued) 16 MEMORY OP LOCATION CODE 0010 653C; 0012 ...
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Programming Example for Division MEMORY OP LOCATION CODE 0000 ; 0000 ; 0000 ; 0000 68C22000; 0004 ; 0004 68C33000; 0008 ; 0008 68C44000; 000C ; 000C ; 000C E067F0; 000F ; 000F ; 000F ; 000F E464; 0011 ; ...
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Dynamic Electrical Specifications (NOTE 1) PARAMETER OPERATION TIMING Maximum Clock Frequency (Note 3) Maximum Shift Frequency (1 Device) (Note 4) Minimum Clock Width t CLK0 t CLK1 Minimum Clock Period t CLK Clock to Shift Propagation t CSH Delay Minimum ...
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Dynamic Electrical Specifications (NOTE 1) PARAMETER WRITE CYCLE Minimum Clear Pulse Width t CLR Minimum Write Pulse Width t WW Minimum Data-In-Setup t DSU Minimum Data-In-Hold t DH Minimum Address to Write t ASU Setup Minimum Address after t AH ...
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Dynamic Electrical Specifications C = 100pF (See Figure 9) (Continued) L (NOTE 1) PARAMETER Strobe to Data Access t SA Minimum Strobe Width t SW NOTES: 1. Maximum limits of minimum characteristics are the values above which all devices function. ...
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... All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...