CS82C37A-5 Harris Corporation, CS82C37A-5 Datasheet

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CS82C37A-5

Manufacturer Part Number
CS82C37A-5
Description
CS82C37A-5CMOS High Performance Programmable DMA Controller
Manufacturer
Harris Corporation
Datasheet

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS82C37A-5
Manufacturer:
HARRIS
Quantity:
5 510
Part Number:
CS82C37A-5
Quantity:
5 510
March 1997
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
Features
• Compatible with the NMOS 8237A
• Four Independent Maskable Channels with Autoinitial-
• Cascadable to any Number of Channels
• High Speed Data Transfers:
• Memory-to-Memory Transfers
• Static CMOS Design Permits Low Power Operation
• Fully TTL/CMOS Compatible
• Internal Registers may be Read from Software
Ordering Information
CP82C37A-5
IP82C37A-5
CS82C37A-5
IS82C37A-5
CD82C37A-5
ID82C37A-5
MD82C37A-5/B
5962-9054301MQA
MR82C37A-5/B
5962-9054301MXA
ization Capability
- Up to 4MBytes/sec with 8MHz Clock
- Up to 6.25MBytes/sec with 12.5MHz Clock
- ICCSB = 10 A Maximum
- ICCOP = 2mA/MHz Maximum
5MHz
CP82C37A
IP82C37A
CS82C37A
IS82C37A
CD82C37A
ID82C37A
MD82C37A/B
5962-9054302MQA
MR82C37A/B
5962-9054302MXA
PART NUMBER
|
Copyright
8MHz
©
Intersil Corporation 1999
CP82C37A-12
IP82C37A-12
CS82C37A-12
IS82C37A-12
CD82C37A-12
ID82C37A-12
MD82C37A-12/B
5962-9054303MQA
MR82C37A-12/B
5962-9054303MXA
12.5MHz
4-192
Description
The 82C37A is an enhanced version of the industry standard
8237A Direct Memory Access (DMA) controller, fabricated
using Intersil’s advanced 2 micron CMOS process. Pin
compatible with NMOS designs, the 82C37A offers
increased
dramatically reduced power consumption. The fully static
design permits gated clock operation for even further
reduction of power.
The 82C37A controller can improve system performance by
allowing external devices to transfer data directly to or from
system memory. Memory-to-memory transfer capability is
also provided, along with a memory block initialization fea-
ture. DMA requests may be generated by either hardware or
software, and each channel is independently programmable
with a variety of features for flexible operation.
The 82C37A is designed to be used with an external
address latch, such as the 82C82, to demultiplex the most
significant 8-bits of address. The 82C37A can be used with
industry standard microprocessors such as 80C286, 80286,
80C86, 80C88, 8086, 8088, 8085, Z80, NSC800, 80186 and
others. Multimode programmability allows the user to select
from three basic types of DMA services, and reconfiguration
under program control is possible even with the clock to the
controller stopped. Each channel has a full 64K address and
word count range, and may be programmed to autoinitialize
these registers following DMA termination (end of process).
40 Ld PDIP
44 Ld PLCC
40 Ld CERDIP
44 Pad CLCC
SMD#
SMD#
PACKAGE
Programmable DMA Controller
functionality,
CMOS High Performance
82C37A
improved
TEMPERATURE
-55
-55
-40
-40
-40
0
0
0
o
o
o
o
o
o
o
o
C to +70
C to +70
C to +70
C to +125
C to +125
RANGE
C to +85
C to +85
C to +85
File Number
performance,
o
o
o
o
o
o
C
C
C
o
o
C
C
C
C
C
E40.6
E40.6
N44.65
N44.65
F40.6
F40.6
F40.6
F40.6
J44.A
J44.A
PKG. NO.
2967.1
and

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CS82C37A-5 Summary of contents

Page 1

... Static CMOS Design Permits Low Power Operation - ICCSB = 10 A Maximum - ICCOP = 2mA/MHz Maximum • Fully TTL/CMOS Compatible • Internal Registers may be Read from Software Ordering Information PART NUMBER 5MHz 8MHz CP82C37A-5 CP82C37A IP82C37A-5 IP82C37A CS82C37A-5 CS82C37A IS82C37A-5 IS82C37A CD82C37A-5 CD82C37A ID82C37A-5 ID82C37A MD82C37A-5/B MD82C37A/B 5962-9054301MQA 5962-9054302MQA MR82C37A-5/B ...

Page 2

Pinouts 82C37A (PDIP/CERDIP) TOP VIEW IOR 1 IOW 2 MEMR 3 MEMW READY 6 HLDA 7 ADSTB 8 AEN 9 HRQ CLK 12 RESET 13 DACK2 14 DACK3 15 DREQ3 16 DREQ2 17 DREQ1 ...

Page 3

Pin Description PIN SYMBOL NUMBER TYPE decoupling. GND 20 Ground CLK 12 I CLOCK INPUT: The Clock Input is used to generate the timing signals which control 82C37A operations. This input may be driven from ...

Page 4

Pin Description (Continued) PIN SYMBOL NUMBER TYPE EOP 36 I/O END OF PROCESS: End of Process (EOP active low bidirectional signal. Information concerning the completion of DMA services is available at the bidirectional EOP pin. The 82C37A allows ...

Page 5

Functional Description The 82C37A direct memory access controller is designed to improve the data transfer rate in systems which must transfer data from an I/O device to memory, or move a block of memory to an I/O device. It will ...

Page 6

The 82C37A can assume seven separate states, each composed of one full clock period. State I (SI) is the idle state entered when the 82C37A has no valid DMA requests pending, at the end of a transfer sequence, ...

Page 7

DMA requests of the additional device to propagate through the priority network circuitry of the preceding device. The priority chain is preserved and the new device must wait for its turn to acknowledge requests. Since ...

Page 8

S24 state). It should be noted that an external EOP cannot cause the channel 0 Address and Word Count registers to autoinitialize, even if the Mode register is programmed for autoinitialization. An external EOP will autoinitialize the channel 1 registers, ...

Page 9

Current Word Count Register - Each channel has a 16-bit Current Word Count register. This register determines the number of transfers to be performed. The actual number of transfers will be one more than the number programmed in the Current ...

Page 10

Mask Register - Each channel has associated with it a mask bit which can be set to disable an incoming DREQ. Each mask bit is set when its associated channel produces an EOP if the channel is not programmed to ...

Page 11

Software Commands There are special software commands which can be executed by reading or writing to the 82C37A. These com- mands do not depend on the specific data pattern on the data bus, but are activated by the I/O operation ...

Page 12

Application Information Figure 6 shows an application for a DMA system utilizing the 82C37A DMA controller and the 80C88 Microprocessor. In this application, the 82C37A DMA controller is used to improve system performance by allowing an I/O device to transfer ...

Page 13

Figure 7 shows an application for a DMA system using the 82C37A DMA controller and the 80C286 Microprocessor. In this application, the system clock comes from the 82C284 clock generator PCLK signal which is inverted to provide proper READY setup ...

Page 14

Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 15

AC Electrical Specifications SYMBOL PARAMETER DMA (MASTER) MODE (1)TAEL AEN HIGH from CLK LOW (S1) Delay Time (2)TAET AEN LOW from CLK HIGH (SI) Delay Time (3)TAFAB ADR Active to Float Delay from CLK ...

Page 16

AC Electrical Specifications SYMBOL PARAMETER (21)TEPW EOP Pulse Width (22)TFAAB ADR Valid Delay from CLK HIGH (23)TFAC READ or WRITE Active from CLK HIGH (24)TFADB DB Valid Delay from CLK HIGH (25)THS HLDA Valid ...

Page 17

AC Electrical Specifications SYMBOL PARAMETER (62)TDVWL DACK Valid to WRITE LOW (63)TRHDI READ HIGH to DACK Inactive (64)TAZRL ADR Float to READ LOW PERIPHERAL (SLAVE) MODE (41)TAR ADR Valid or CS LOW to READ ...

Page 18

Timing Waveforms CS TCWL (43) IOW TAWL (42 DB0 - DB7 NOTE: Successive WRITE accesses to the 82C37A must allow at least TCY as recovery time between accesses. A TCY recovery time must be allowed before executing ...

Page 19

Timing Waveforms (Continued CLK TQS (30) DREQ TDQ (18) HRQ THS (25) HLDA TAEL AEN TCLSH (33) ADSTB DB0-DB7 A0-A7 DACK READ WRITE (FOR EXTENDED WRITE) INT EOP EXT EOP 82C37A ...

Page 20

Timing Waveforms (Continued) S0 S11 S12 CLK (33) (34) TCLSL TCLSH ADSTB TFAAB (22) TASS (11) A0-A7 TFADB (24) DB0-DB7 A8-A15 TDCL (15) TFAC (23) MEMR TFAC (23) MEMW EOP EXT EOP S2 CLK READ WRITE EXTENDED WRITE READY NOTE: ...

Page 21

Timing Waveforms (Continued) CLK A0-A7 READ WRITE READY V CC RESET IOR OR IOW AC Test Circuits V1 R1 OUTPUT FROM DEVICE UNDER TEST C1 (NOTE) NOTE: Includes STRAY and FIXTURE Capacitance TEST CONDITION DEFINITION TABLE PINS V1 All Outputs ...

Page 22

Burn-In Circuits VCC DO5 VCC/2 VCC/2 VCC/2 DO5 VCC/2 VCC/2 VCC/2 DO5 DO6 VCC/2 VCC/2 F12 F13 F14 F15 GND OPEN OPEN DO5 VCC/2 VCC/2 VCC/2 DO5 F1 D06 VCC/2 OPEN NOTES 5.5V 0. VIH ...

Page 23

Die Characteristics DIE DIMENSIONS: 148 x 159 x 19 1mils (3760- x 4040 x 525 m) METALLIZATION: Type: SiAlCu Å Å Thickness: Metal 1: 8k 0.75k Å Å Thickness: Metal 2: 12k 1.0k Metallization Mask Layout All Intersil semiconductor products ...

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