HY628400ALLT2-55

Manufacturer Part NumberHY628400ALLT2-55
DescriptionHY628400ALLT2-55512K x8 bit 5.0V Low Power CMOS slow SRAM
ManufacturerHynix Semiconductor
HY628400ALLT2-55 datasheet
 


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DATA RETENTION ELECTRIC CHARATERISTIC

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Notes:
1. A write occurs during the overlap of a low /WE and a low /CS.
2. tWR is measured from the earlier of /CS or /WE going high to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the
output must not be applied.
4. If the /CS low transition occur simultaneously with the /WE low transition or after the
/WE transition, outputs remain in a high impedance state.
5. Q(data out) is the same phase with the write data of this write cycle.
6. Q(data out) is the read data of the next address.
7. Transition is measured + 200mV from steady state.
This parameter is sampled and not 100% tested.
8. /CS in high for the standby, low for active

DATA RETENTION ELECTRIC CHARATERISTIC

= 0¡ É to 70¡ É ( Normal)/-25 C to 85 C (Extended) /-40 C to 85 C (Industrial), unless otherwise specified.
T
A
Symbol
Parameter
V
Vcc for Data Retention
DR
I
Data Retention Current
CCDR
tCDR
Chip Deselect to Data
Retention Time
tR
Operating Recovery Time
Notes:
1. Typical values are at the condition of T
2. tRC is read cycle time.
DATA RETENTION TIMING DIAGRAM
VCC
4.5V
tCDR
2.2V
VDR
/CS
VSS
Rev 07 / Apr. 2001
Test Condition
/CS > Vcc - 0.2V,
V
> Vcc - 0.2V or V
< Vss + 0.2V
IN
IN
Vcc = 3.0V,
/CS1>Vcc - 0.2V,
V
> Vcc - 0.2V or
IN
V
< Vss + 0.2V
IN
= 25 C.
A
DATA RETENTION MODE
tR
/CS > VCC-0.2V
HY628400A Series
Min
Typ
Max
2.0
-
-
L
-
-
50
LL
-
-
20
L-E/I
-
-
50
LL-E/I
-
-
30
0
-
-
tRC
-
-
(2)
7
Unit
V
uA
uA
uA
uA
ns
ns