HYB25D128323C-3.3 Infineon Technologies AG, HYB25D128323C-3.3 Datasheet
HYB25D128323C-3.3
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HYB25D128323C-3.3 Summary of contents
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... Edition 2003-07 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany Infineon Technologies AG 2003. © All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein ...
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... HYB25D128323C[-3/-3.3], HYB25D128323C[-3.6/L3.6], HYB25D128323C[-4.5/L4.5], HYB25D128323C-5 Revision History: V1.7 Previous Version: V1.51 Page Subjects (major changes since last revision) all new data sheet template 43 AC Operation Conditions: Input Slew Rate added 46 Timing Parameters for speed sorts –3, –3.3, –3.6, –4.5, and 48 Timing Parameters for speed sorts L3.6 and Previous Version: V1 ...
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... Read Interrupted by a Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.6.4 Write Interrupted by a Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.6.5 Write Interrupted by a Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.6.6 Write Interrupted by a Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.7 Operations and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.8 Function Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.9 DDR SGRAM Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] 5 V1.7, 2003-07 ...
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... Read interrupted by Write Figure 26 Read interrupted by Precharge Figure 27 Write interrupted by Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 28 Write interrupted by Read Figure 29 Write interrupted by Precharge Figure 30 DDR SGRAM Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 31 Output Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 32 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] 6 V1.7, 2003-07 ...
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... Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] 7 V1.7, 2003-07 ...
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... Timing Parameters for speed sorts –3, –3.3, –3.6, –4.5, and – Table 18 Timing Parameters for speed sorts L3.6 and L4 Table 19 HYB25D128323C– Table 20 HYB25D128323C–3 Table 21 HYB25D128323C–3 Table 22 HYB25D128323C–4 Table 23 HYB25D128323C– Table 24 HYB25D128323CL3 Table 25 HYB25D128323CL4 Table 26 Operating Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] 8 V1.7, 2003-07 ...
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... I/O pins. A single Read or Write access to the DDR Data Sheet = = < modes DD –3 –3.3 –3.6 –4.5 3 3.3 3.6 4.5 333 300 278 222 4.0 4.0 4.2 4.5 250 250 238 222 1.05 1.15 1.26 1.58 0.30 0.30 0.33 0.45 9 HYB25D128323C[-3/-3.3] HYB25D128323C[-3.6/L3.6] HYB25D128323C[-4.5/L4.5] HYB25D128323C-5 –5.0 L3.6 L4.5 Unit 5.0 3.6 4.5 ns 200 278 222 MHz 5.0 4.2 4.5 ns 200 238 222 MHz 1.75 1.26 1.58 ns 0.5 0.33 0.45 ns 4096 rows V1.7, 2003-07 256 ...
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... A standard JEDEC TF-XBGA 128 package is used which enables ultra high speed clock and data transfer rates. The signals are mapped symmetrically to the balls in order to enable mirrored mounting in application. The chip is fabricated in Infineon technologies advanced 256M process technology. Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] 10 Overview ...
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... CAS# WE# K RAS CS Figure 1 Ball Out 128Mbit DDR SGRAM Note: The inner matrix balls will be used as thermal total amount of balls is 144 Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4. SSQ DDQ ...
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... Data Input/Output: The DQx signals form the 32 bit wide data bus. At READ cycles the pins are outputs and during WRITE cycles inputs. The data is transferred at both edges of the DQSx signals. Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] 12 Pin Configuration ...
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... DDQ, SSQ improved noise immunity. NC, RFU – Please do not connect No Connect, Reserved for Future Use pins. MCL – Must be connected to low Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4. the reference voltage input signal. REF V < 2.9 V for –3.6 and L3 < 2.9 V for –3 and –3 2.5V ± ...
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... Column Addresses A7-A0, AP Column Address Buffer Column Address Counter Row Decoder Memory Array Bank 0 4096 x 256 x 32 bit Figure 2 Functional blocks Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] Row Addresses A11-A0, BA1-BA0 Row Decoder Memory Array Bank 1 4096 x 256 x 32 bit Input Buffers Output Buffers DQ31-DQ24 DQ23-DQ16 ...
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... A10 0 0 RFU RFU Extended Mode Register Access BA0 Accessed Register 0 Mode Register 1 Extend. Mode Reg. DLL Reset Figure 3 Mode Register Bitmap Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4. RFU DLL TM CAS Latency Testmode A7 mode 0 Normal 1 Testmode CAS Latency DLL Reset ...
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... Extended Mode Register Setup (EMRS) The Extended Mode Register is responsible for enabling / disabling the DLL in the HYB25D128323C and for selecting the interface type for the IOs and input pins. The Extended Mode Register can be programmed by performing a normal Mode Register Setup operation and setting the BA0 bit to high. All other bits of the EMRS register are reserved and should be set to low ...
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... CLK and CLK# signal. The between the data strobe edge and the output data edge. The following table summarizes the mapping of DQSx and DMx signals to the data bus. Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [ The maximum value for ...
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... The input data is masked in the same cycle when the corresponding DMx signal is high DMDQSS DMDQSH (i.e. the DMx mask to write latency is zero.) Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] data mask signal DM0 DM1 DM2 DM3 ...
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... DDR SGRAM, data is written with a delay which is defined by the parameter different than the single data rate SGRAM where data is written in the same cycle as the Write command is issued. CLK, CLK# WR DQSx t WPRES DQx Figure 8 DQS Pre/Postamble at Write Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4. DMDQSS t DMDQSH t QDQSH Q Q ...
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... Clk Command Figure 10 Mode Register Set Timing 3.5.3 Extended Mode Register Set Timing The timing of the Extended Mode Register Setup operation is equivalent to the Mode Register Setup timing. Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4. apply V before or at the same time as DDQ DDQ DLL EMRS ...
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... Precharge command at the rising edge of the clock. The Precharge command can be used to precharge each bank respectively or all banks simultaneously. The Bank addresses BA0 and BA1 select the bank to be precharged. After a Precharge command, the analog delay be initiated to the same bank. Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] t min. for write commands). Once a bank has been activated, RCDWR READ ...
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... Self Refresh operation to reduce power. An internal timing generator guarantees the self refreshing of the memory content. To exit the Self Refresh mode, a stable external clock is needed for the DLL before returning CKE high. After the Power Down Exit time held high for longer than SREX Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] BA0 ...
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... During Power Down Mode, refresh operations cannot be performed; therefore, the device cannot remain in Power Down Mode longer than the refresh period ( the device. REF Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] SELF NOP NOP NOP REFRESH DESEL ...
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... Mode Register. The first data after the READ command is available depending on the CAS latency. The subsequent data is clocked out on the rising and falling edge of DQSx until the burst is completed. The DQSx signal is generated by the DDR SGRAM during Burst Read Operations. Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] NOP NOP DESEL ...
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... DQSx following the WRITE command. The time between the WRITE command and the first corresponding edge of the data strobe is rising and falling edge of the data strobe until the burst length is completed. When the burst has been finished, any additional data supplied to the DQ pins will be ignored. Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] NOP NOP NOP NOP ...
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... CAS Latency set in the Mode Register. The Burst Stop latency is equal to the CAS latency CL.The Burst Stop command is not supported during a write burst operation. Burst Stop is also illegal during Read with Auto-Precharge. Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] WRITE NOP NOP ...
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... The DDR SGRAM has a Data Mask function that can be used only during write cycles. When the Data Mask is activated (DMx high) during burst write, the write operation is masked immediately. The DMx to data-mask latency is zero. DMx can be issued at the rising or falling edge of Data Strobe. Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] NOP NOP NOP ...
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... Once the precharge operation has started, the bank cannot be reactivated and the new command can not be asserted until the Precharge time ( has been satisfied. Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] NOP NOP NOP ...
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... DQSx CAS latency = 2 DQx DQSx CAS latency = 3 DQx DQSx CAS latency = 4 DQx Begin of Burst length = 4 Autoprecharge Figure 21 Read Burst with Autoprecharge Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] NOP NOP NOP NOP D-out D-out D-out D-out D-out D-out D-out D-out 2 ...
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... Once the precharge operation has started, the bank cannot be reactivated and the new WR command can not be asserted until the Precharge time ( yet, an internal interlock will delay the precharge operation until it is satisfied. Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] CAS latency = READ A ...
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... A Burst Read can be interrupted before completion of the burst by a new Read command given to any bank. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read command continues to appear on the outputs until the CAS latency from the Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4. ...
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... Burst Stop command must be applied at least 3 clock cycles for least 4 clock cycles for least 5 clock cycles for before the Write command. CLK READ BST Command DQSx DQx Figure 25 Read interrupted by Write Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4. minimum 1 CLK. CCD READ b NOP NOP D-out D-out D-out a0 ...
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... The Write to Write interval (CAS a to CAS b command period) is defined by the parameter CLK Command DQSx DQx Figure 27 Write interrupted by Write Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] . NOP PRE NOP Precharge latency = CL D-out D-out D-out ...
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... A Burst Write operation can be interrupted before completion of the burst by a Precharge of the same bank. Random column access is allowed. A Write Recovery time ( command. When Precharge command is asserted, any residual data from the burst write cycle must be masked by DMx. Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] NOP Read Last valid t ...
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... Write Command WRITE Write Command with WRITEA Auto Precharge Burst Stop BST Precharge Single Bank PRE Precharge All Banks PREAL Auto Refresh AREF Self Refresh Entry SREFEN Self Refresh Exit SREFEX Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] NOP NOP Last valid t WR data D-in D-in D-in D-in D-in D- ...
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... No Operation CA Column Address Ax Address Line x Table 11 Function Truth Table I Current State Command IDLE DESEL NOP BST READ / READA WRITE / WRITEA ACT PRE / PREAL AREF / SREF MRS / EMRS Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] CKE CKE CS# RAS# CAS# WE# n ...
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... PRE / PREAL AREF / SREF MRS / EMRS WRITE DESEL NOP BST READ / READA WRITE / WRITEA ACT PRE / PREAL AREF / SREF MRS / EMRS Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] Address Action X NOP X NOP X NOP BA, CA, A8 Begin Read, Determine Auto Precharge BA, CA, A8 Begin Write, Determine Auto Precharge BA, RA ...
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... PRE / PREAL AREF / SREF MRS / EMRS WRITE DESEL RECOVERING NOP BST READ / READA WRITE / WRITEA ACT PRE / PREAL AREF / SREF MRS / EMRS Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] Address Action X Continue burst to end, Precharge X Continue burst to end, Precharge X ILLEGAL BA, CA, A8 ILLEGAL BA, CA, A8 ILLEGAL BA, RA ILLEGAL ...
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... RCD t 10) Illegal not satisfied 11) Illegal not satisfied. RC Note: All entries assume the CKE was High during the preceding clock cycle Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] Address Action X NOP (Precharge after X NOP (Precharge after X NOP (Precharge after BA, CA, A8 ILLEGAL BA, CA, A8 ...
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... CKE low-to-high transition re-enables inputs asynchronously. A minimum setup time to CLK must be satisfied before any commands other than EXIT are executed. 2) Power Down can be entered when all banks are idle (banks can be active or precharged) 3) Self Refresh can be entered only from the Precharge / Idle state. Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] RAS CAS WE# Address Action ...
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... DDR SGRAM Simplified State Diagram MODE MRS REGISTER SET WRITE WRITE WRITEA WRITEA POWER PRE ON Figure 30 DDR SGRAM Simplified State Diagram Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] SELF REFRESH SREFEN SREFEX AUTO AREF IDLE REFRESH CKEL CKEH ACT CKEH CKEL ROW ACTIVE READ WRITEA ...
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... High Current -0,373V OUT DDQ Low Current 0.373V OUT Output Levels: SSTL2 Weak Mode 2.5V High Current – 0,373V OUT DDQ Low Current 0.373V OUT Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] Symbol Values min. typ –0.5 – IN OUT V –0.5 – – ...
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... Clock Input Crossing Point (CLK/CLK) I/O Reference Voltage Input Slew Rate Figure 31 Output Test Circuit Table 16 Pin Capacitances Pin A11.. A0, BA1, BA0, CKE, CS, CAS, RAS, WE CLK, CLK Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4. modes: 2.5V 5% and 2.5V – 2. the transmitting device. DDQ V may not exceed 2% ...
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... Row Precharge 12 RP Time Activate( 9.0 RRD Activate(b) Command period CAS(a) to CAS( CCD Command period Last data in to Active t 6 DAL + ( Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] min. 1.0 1.0 –3.3 –3.6 MIM MIM 5.0 3.3 5.0 3.6 5.0 4.0 5.0 4.2 333 200 300 200 250 200 250 200 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 t ...
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... Data Mask to DQS t 0.40 — DMDQSH Hold Time t Clock to DQS Write 0 WPRES Preamb. Setup Time t Clock to DQS Write 0.25 — WPREH Preamble Hold Time t DQS Write 0.4 WPST Postamble Hold Time t Write Recovery 2 WR Time Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] –3.3 –3.6 MIM MIM +0.5 -0.5 +0.5 -0.55 +0.55 -0.7 +0.5 -0.5 +0.5 -0.55 +0.55 -0.7 0.9 0.7 0.9 0.7 1.1 0.8 1.1 0.8 — 4 — 4 +0.3 — ...
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... The Write Recovery Time starts at the first rising edge of clock after the last valid (falling) DQS edge of the slowest DQS signal. Table 18 Timing Parameters for speed sorts L3.6 and L4.5 Part Number Extension Interface Parameter Clock and Clock Enable Clock Cycle Time System frequency Clock high level width Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] –3.3 –3.6 MIM MIM — 1 — 1 — 0.35 0.65 0.35 0.65 ...
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... Data Mask to DQS Setup Time Data Mask to DQS Hold Time Clock to DQS Write Preamb. Setup Time Clock to DQS Write Preamble Hold Time DQS Write Postamble Hold Time Write Recovery Time Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] L3.6 L4.5 MIM WM/MIM Symbol min. ...
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... The Write Recovery Time starts at the first rising edge of clock after the last valid (falling) DQS edge of the slowest DQS signal. Table 19 HYB25D128323C–3 t Frequency / CAS latency CK 333 MHz / 3 300 MHz / 3 278 MHz / 3 250 MHz / 4 222 MHz / 4 200 MHz / 5 Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] L3.6 MIM Symbol min WTR t 0.35 DQSH t 0.35 DQSL t — REF t — REFC t — ...
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... CAS latency CK 222 MHz / 4 200 MHz / 5 183 MHz / 5 Table 23 HYB25D128323C–5 t Frequency / CAS latency CK 200 MHz / 5 183 MHz / 5 Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [ RFC RAS RP WR RRD ...
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... RC RC(min 0mA; Address and CK CK(min.) OUT control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle power-down mode CK(min.) CKE=LOW Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4. RFC RAS ...
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... Auto Precharge RC(min Address and control CK CK(min.) inputs change only during Active, READ, or WRITE commands 1) Measured with output open. Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] Symbol –3 –3.3 –3.6 –4.5 –5.0 L3.6 L4.5 Unit Notes max. I 130 120 110 DD2F DD3P ; ...
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... The package is conforming with JEDEC MO-205 Variation BD General Tolerances according to ISO 8015 The inner matrix of 4 × 4 balls is reserved for thermal contacts 1.50 1.44 1.36 0 0.85 MAX All dimensions in mm. Notation is TYP MIN Figure 32 Package Outlines Data Sheet HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 11.1 10.9 11.1 10.9 8.8 8.8 0.8 -- MAX or or TYP MIN 52 128 Mbit DDR SGRAM [4M x 32] Package Outlines 8.8 8 ...
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... Published by Infineon Technologies AG ...