HYB39S128160CT-7 Infineon Technologies AG, HYB39S128160CT-7 Datasheet
HYB39S128160CT-7
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HYB39S128160CT-7 Summary of contents
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Synchronous DRAM • High Performance: -7 -7.5 -8 Units f 143 133 125 MHz 7 CK3 t 5.4 5 AC3 t 7 CK2 t 5 AC2 ...
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Ordering Information Type Function Code Package HYB 39S128400CT-7 PC133-222-520 P-TSOP-54 (400mil) HYB 39S128400CT-7.5 PC133-333-520 P-TSOP-54 (400mil) HYB 39S128400CT-8 PC100-222-620 P-TSOP-54 (400mil) HYB 39S128800CT-7 PC133-222-520 P-TSOP-54 (400mil) HYB 39S128800CT-7.5 PC133-333-520 P-TSOP-54 (400mil) HYB 39S128800CT-8 PC100-222-620 P-TSOP-54 (400mil) HYB 39S128160CT-7 PC133-222-520 P-TSOP-54 ...
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DQ0 DQ0 N. DDQ DDQ DDQ DQ1 N.C. N.C. DQ2 DQ1 DQ0 SSQ SSQ SSQ DQ3 N.C. N.C. DQ4 DQ2 N. DDQ DDQ DDQ DQ5 ...
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Functional Block Diagrams Column Addresses A0 - A9, A11, AP, BA0, BA1 Column Address Column Address Counter Buffer Row Decoder Memory Array Bank 0 4096 x 2048 x 4 Bit Input Buffer Output Buffer DQ0 - DQ3 Block Diagram: 32M ...
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Column Addresses A0 - A9, AP, BA0, BA1 Column Address Column Address Counter Buffer Row Decoder Memory Array Bank 0 4096 x 1024 x 8 Bit Input Buffer Output Buffer DQ0 - DQ7 Block Diagram: 16M x8 SDRAM (12 / ...
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Column Addresses A0 - A8, AP, BA0, BA1 Column Address Column Address Counter Buffer Row Decoder Memory Array Bank 0 4096 x 512 4096 x 512 x 16 Bit Input Buffer Output Buffer DQ0 - DQ15 Block Diagram: 8M x16 ...
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Signal Pin Description Pin Type Signal Polarity Function CLK Input Pulse Positive Edge CKE Input Level Active High CS Input Pulse Active Low RAS Input Pulse Active CAS Low A11 Input Level – BA0, BA1 Input Level ...
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Signal Pin Description (cont’d) Pin Type Signal Polarity Function DQM Input Pulse Active LDQM High UDQM V Supply – – Supply – – DDQ V SSQ INFINEON Technologies HYB 39S128400/800/160CT(L) 128-MBit Synchronous DRAM The Data Input/Output ...
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Operation Definition All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the positive edge of the clock. The following list shows the truth table for the operation commands. Operation Device CKE ...
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Address Inputs for Mode Register Set Operation BA1 BA0 A11 A10 Operation Mode Operation Mo de BA1 BA0 M11 M10 ...
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Power On and Initialization The default power on state of the mode register is supplier specific and may be undefined. The following power on and initialization sequence guarantees the device is preconditioned to each users specific needs. Like a conventional ...
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In other words, unlike burst length and 8, full page burst continues until it is terminated using another command. Similar to the page mode of conventional DRAM’s, burst read or ...
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A minimum RC refresh mode. The same rule applies to any access command after the automatic refresh operation. The chip has an on-chip timer and the Self Refresh mode is available. It enters the mode when ...
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Bank Selection by Address Bits A10 BA0 BA1 Bank Bank Bank Bank all Banks Burst Termination Once a burst read or ...
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Electrical Characteristics Absolute Maximum Ratings Operating Temperature Range....................................................................................... Storage Temperature Range .................................................................................. – 150 C Input/Output Voltage ......................................................................................... – 0.3 to Power Supply Voltage .............................................................................. – 0 4.6 ...
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Operating Currents 3 (Recommended Operating Conditions unless otherwise noted) Parameter & Test Condition Operating current – All banks operated CK CK(MIN.), in random access,all ...
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AC Characteristics 3 Parameter Symb. Clock and Clock Enable Clock Cycle Time CAS Latency = CAS Latency = 2 ...
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AC Characteristics (cont’ 3 Parameter Symb. Refresh Cycle Refresh Period t REF (4096 cycles) Self Refresh Exit Time t SREX Read Cycle ...
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CLOCK HOLD t SETUP INPUT 1 OUTPUT 3. If clock rising time is longer than 1 ns, a time ( longer than 1 ns, a time ...
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Package Outlines Plastic Package, P-TSOPII-54 ( 400 mil, 0.8 mm lead pitch ) Thin Small Outline Package, SMD 0.8 26x 0.8 = 20.8 3) +0.1 0.35 -0. 2.5 max 1) 22.22 ±0.13 Index Marking 1) Does not include ...
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Timing Diagrams 1. Bank Activate Command Cycle 2. Burst Read Operation 3. Read Interrupted by a Read 4. Read to Write Interval 4.1 Read to Write Interval 4.2 Minimum Read to Write Interval 4.3 Non-Minimum Read to Write Interval 5. ...
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Bank Activate Command Cycle (CAS latency = CLK Bank B Address Row Addr. Bank B Command NOP Activate "H" or "L" 2. Burst Read Operation (Burst Length = 4, CAS latency = ...
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Read Interrupted by a Read (Burst Length = 4, CAS latency = CLK Command Read A Read B CAS latency = DQ’s CK2 CAS latency = DQ’s CK3 4. ...
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Minimum Read to Write Interval (Burst Length = 4, CAS latency = CLK DQM Command NOP NOP CAS latency = DQ’s CK2 "H" or "L" Non-Minimum Read to Write Interval ...
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Burst Write Operation (Burst Length = 4, CAS latency = CLK Command NOP Write A DQ’s DIN A0 The first data element and the Write are registered on the same clock edge. INFINEON Technologies T2 ...
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Write and Read Interrupt 6.1 Write Interrupted by a Write (Burst Length = 4, CAS latency = CLK 1 Clk Interval Command NOP Write A 1 Clk Interval DQ’s DIN A0 6.2 Write Interrupted by ...
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Burst Write and Read with Auto Precharge 7.1 Burst Write with Auto-Precharge (Burst Length = 2, CAS latency = CLK CAS Latency = 2: Bank A Command NOP Active DQ’s CAS Latency = 3: ...
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AC Parameters 8.1 AC Parameters for a Write Timing CLK CK2 t CL CKE t CKS RAS CAS RAx t AS ...
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AC Parameters for a Read Timing CLK CK2 t CL CKE CKS RAS CAS RAx t AS Addr. RAx DQM Hi-Z DQ ...
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Mode Register Set CLK CKE CS RAS CAS Address Key Addr. Precharge Command All Banks Mode Register Set Command INFINEON Technologies T10 T11 T12 T13 t ...
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Power on Sequence and Auto Refresh (CBR CLK CKE High Level is required CS RAS CAS Addr. DQM t RP Hi-Z DQ Precharge Command All Banks Inputs must be 1st Auto ...
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Clock Suspension ( Using CKE) 11.1 Clock Suspension During Burst Read CAS Latency = CLK t CK2 CKE CS RAS CAS RAx Addr. RAx CAx DQM Hi-Z DQ Activate Read ...
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Clock Suspension During Burst Read CAS Latency = CLK t CK3 CKE CS RAS CAS RAx Addr. RAx CAx DQM Hi-Z DQ Activate Read Command Command Bank A Bank A ...
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Clock Suspension During Burst Write CAS Latency = CLK t CK2 CKE CS RAS CAS RAx Addr. RAx CAx DQM Hi-Z DQ DAx0 DAx1 Activate Clock Command Suspend Bank A ...
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Clock Suspension During Burst Write CAS Latency = CLK t CK3 CKE CS RAS CAS WE BA A8/AP RAx Addr. RAx CAx DQMx Hi-Z DQ DAx0 Activate Clock Command Suspend Bank A 1 ...
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Power Down Mode and Clock Suspend CLK t CKS t CK2 CKE CS RAS CAS RAx Addr. RAx DQM Hi-Z DQ Activate Active Command Standby Bank A Clock Suspend Clock Suspend ...
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Self Refresh (Entry and Exit CLK CKE t CKS CS RAS CAS Addr. DQM Hi-Z DQ All Banks Self Refresh must be idle Entry INFINEON Technologies ...
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Auto Refresh (CBR CLK t CK2 CKE CS RAS CAS Addr. t (Minimum Interval) RP DQM Hi-Z DQ Precharge Auto Refresh Command Command All Banks INFINEON Technologies ...
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Random Column Read (Page within same Bank) 15.1 CAS Latency = CLK t CK2 CKE CS RAS CAS RAw Addr. RAw CAw DQM Activate Read Command Command ...
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CAS Latency = CLK t CK3 CKE CS RAS CAS RAw Addr. RAw CAw DQM Activate Read Command Command Bank A Bank A INFINEON Technologies T5 T6 ...
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Random Column write (Page within same Bank) 16.1 CAS Latency = CLK t CK2 CKE CS RAS CAS RBw Addr. RBw CBw DQM DBw0 DBw1 DBw2 Activate ...
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CAS Latency = CLK t CK3 CKE CS RAS CAS RBz Addr. RBz CBz DQM DBw0 DBw1 DBw2 Activate Write Command Command Bank B Bank B INFINEON ...
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Random Row Read (Interleaving Banks) with Precharge 17.1 CAS Latency = CLK t CK2 High CKE CS RAS CAS RBx Addr. RBx CBx t RCD DQM t AC2 Hi-Z Bx0 ...
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CAS Latency = CLK t CK3 CKE High CS RAS CAS RBx Addr. RBx CBx t RCD DQM Hi-Z DQ Activate Read Command Command Bank B Bank B INFINEON Technologies ...
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Random Row Write (Interleaving Banks) with Precharge 18.1 CAS Latency = CLK t CK2 High CKE CS RAS CAS RAx Addr. RAx CAx t RCD DQM Hi-Z DQ DAx0 DAx1 ...
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CAS Latency = CLK t CK3 CKE High CS RAS CAS RAx Addr. RAx CAx t RCD DQM Hi-Z DQ DAx0 DAx1 DAx2 Activate Write Command Command Bank A Bank ...
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Precharge termination of a Burst 19.1 CAS Latency = CLK t CK2 CKE High CS RAS CAS RAx Addr. RAx CAx DQM DAx0 DAx1 DAx2 Activate Write ...
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Full Page Burst Operation 20.1 Full Page Burst Read, CAS Latency = CLK t CK2 High CKE CS RAS CAS RAx RBx Addr. RAx CAx RBx DQM Hi ...
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Full Page Burst Operation 20.2 Full Page Burst Write, CAS Latency = CLK t CK3 High CKE CS RAS CAS RAx Addr. RAx CAx DQM Hi-Z DQ Activate Activate Activate ...
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TABLE OF CONTENTS 128-MBit Synchronous DRAM Ordering Information Pin Definitions and Functions Pin Configuration for x4, x8 & x16 Organized 128M-DRAMs Functional Block Diagrams Block Diagram: 32M x4 SDRAM ( addressing Block Diagram: 16M x8 SDRAM ...
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Attention please ! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. This infomation describes the type of components and ...