IDT71V124S20Y

Manufacturer Part NumberIDT71V124S20Y
DescriptionIDT71V124S20Y3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Revolutionary Pinout
ManufacturerIntegrated Device Technology, Inc.
IDT71V124S20Y datasheet
 

Specifications of IDT71V124S20Y

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IDT71V124, 3.3V CMOS Static RAM
1 Meg (128K x 8-Bit), Revolutionary Pinout
Timing Waveform of Write Cycle No.1 (WE Controlled Timing)
ADDRESS
CS
t
AS
WE
DATA
OUT
DATA
IN
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)
ADDRESS
CS
t
AS
WE
DATA
IN
NOTES:
1. A write occurs during the overlap of a LOW CS and a LOW WE.
2. OE is continuously HIGH. During a WE controlled write cycle with OE LOW, t
. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is the specified t
placed on the bus for the required t
DW
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance state. CS must be active during the t
period.
5. Transition is measured ±200mV from steady state.
t
WC
t
AW
(2)
t
WP
(5)
t
WHZ
HIGH IMPEDANCE
(3)
t
WC
t
AW
t
CW
must be greater than or equal to t
WP
6.42
6
Commercial and Industrial Temperature Ranges
(1,2,4)
t
WR
(5)
t
OW
(3)
t
DH
t
DW
DATA
VALID
IN
(1,4)
(3)
t
WR
t
t
DW
DH
DATA
VALID
IN
+ t
to allow the I/O drivers to turn off and data to be
WHZ
DW
(5)
t
CHZ
3484 drw 07
3484 drw 08
.
WP
write
CW