IDT71V124S20Y Integrated Device Technology, Inc., IDT71V124S20Y Datasheet - Page 6

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IDT71V124S20Y

Manufacturer Part Number
IDT71V124S20Y
Description
IDT71V124S20Y3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Revolutionary Pinout
Manufacturer
Integrated Device Technology, Inc.
Datasheet

Specifications of IDT71V124S20Y

Case
SOJ
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Timing Waveform of Write Cycle No.1 (WE Controlled Timing)
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)
NOTES:
1. A write occurs during the overlap of a LOW CS and a LOW WE.
2. OE is continuously HIGH. During a WE controlled write cycle with OE LOW, t
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance state. CS must be active during the t
5. Transition is measured ±200mV from steady state.
IDT71V124, 3.3V CMOS Static RAM
1 Meg (128K x 8-Bit), Revolutionary Pinout
ADDRESS
ADDRESS
DATA
placed on the bus for the required t
period.
DATA
DATA
OUT
WE
WE
CS
CS
IN
IN
DW
. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is the specified t
t
AS
t
AS
(3)
t
WHZ
(5)
t
t
AW
AW
WP
t
t
must be greater than or equal to t
WP
t
WC
t
6.42
CW
WC
6
(2)
HIGH IMPEDANCE
t
t
DATA
DW
DW
DATA
Commercial and Industrial Temperature Ranges
IN
VALID
IN
WHZ
VALID
+ t
t
t
DH
WR
DW
t
t
OW
WR
to allow the I/O drivers to turn off and data to be
(3)
t
(5)
DH
(1,2,4)
(1,4)
(3)
t
CHZ
3484 drw 08
(5)
3484 drw 07
CW
write
WP
.

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